9. First Details Regarding AMD Bulldozer Emerge: 8 Cores with Multithreading, 128-Bit FPU
Advanced Micro Devices is a company that is known for making surprises. Back in 1999 it stunned everyone with its AMD Athlon processor that immediately stole performance crown from Intel Pentium III, in 2003 its AMD Opteron and AMD Athlon 64 chips simply astonished the markets of desktops and servers with performance and features, but in 2007 the firm shocked with underperforming quad-core AMD Opteron and Phenom processors that also contained a translation look aside buffer (TLB) bug. No surprise that all eyes are on the next-generation Bulldozer micro-architecture.
In November ’09 the firm unwrapped virtually the first official details of the forthcoming Bulldozer micro-architecture and implementation and they seemed to be rather impressive!
Based on the information provided by AMD during its annual Analyst Day in November, the first Bulldozer chip code-named Zambezi (which belongs to Orochi family, according to the firm) will feature eight x86 processing engines with a multithreading technology, two 128-bit FMAC floating point units, shared L2 cache, shared L3 cache as well as integrated memory controller. AMD also states that the new CPU will feature “extensive new power management innovations”. The details are still sketchy, but what should we expect from the information about a product due in 2011?
The implementation of 128-bit FMAC is quite logical: AMD’s SSE5 set of extensions do feature 128-bit multimedia instructions as well as 128-bit three-operant instructions. In fact, there is a trend of increasing of precision of floating point instructions, as we can observe from the last decade.
What is important to note is that Intel Corp.’s forthcoming Sandy Bridge processor features Advanced Vector Extensions (AVX), which support 256-bit FP operations, something very progressive. Both AMD and Intel have already released documentation regarding AVX and SSE5 for developers, but Intel managed to unleash a new compiler supporting AVX in June ’09, whereas AMD has not managed to roll-out its SSE5-supporting tool. As a result, the vast majority of developers are already capable of creating AVX-capable software; however, almost no designers can make SSE5-capable programs at the moment.
Obviously, AMD will also support AVX, but its implementation is likely to be less efficient than that from Intel due to lower-bit FP units. Still until we know more about Sandy Bridge as well as clock-speeds of both processors, we can only guess which chip turns out to be faster.