8. Intel to Demonstrate 48-Core Microprocessor
As a part of its Tera-Scale Computing Research, Intel Corp. has been showcasing rather bizarre chips and concepts for a couple of years now. In early December the firm demonstrated its chip with 48 of fully-fledged x86 processing engines. A couple of days later the company announced decision to cancel its first-generation many-core x86-based Larrabee graphics processor. Even though there is no direct correlation between the two events, some believe that the concept chip will influence the future implementations of Larrabee.
The prototype chip – which Intel calls single-chip cloud computer (SSC) – contains 24 tiles with two IA cores per each, which results in 48 cores – the largest number ever placed on a single piece of silicon. Each core can run a separate OS and software stack and act like an individual compute node that communicates with other compute nodes over a packet-based network. Every core sports its own L2 cache and each tile sports a special router logic that allows tiles to communicate with each other. A 24-router mesh network with 256GB/s bisection bandwidth. The processor sports four integrated DDR3 memory controllers, or one controller per twelve cores.
The SCC can run all 48 cores at one time over a range of 25W to 125W and selectively vary the voltage and frequency of the mesh network as well as sets of cores. Each tile (2 cores) can have its own frequency, and groupings of four tiles (8 cores) can each run at their own voltage.
One of the distinct features of the new 48-core experimental chip will be its extreme programmability. Software applications will be able to automatically control the number of cores to use at any given time and operating systems will be able to assign certain cores for auxiliary tasks. Moreover, software will be able to manage power consumption, clock-speed of individual cores or even shut them down when not needed.
The experimental 48-core central processing unit (CPU) will help Intel and software developers to study management and scheduling mechanisms of explicitly multi-core microprocessors in order to get prepared to bring them onto the mass market. Next year, Intel plans to provide software developers more than a hundred of experimental chips for development of new software apps.
Though each core has 2 levels of cache, there is no hardware cache coherence support among cores in order to simplify the design, reduce power consumption and to encourage the exploration of datacenter distributed memory software models, on-chip. Intel researchers have successfully demonstrated message-passing as well as software-based coherent shared memory on the SCC.
The chip does seem to be extremely interesting. According to Intel, the cores are fully-fledged x86 cores and while it is unknown whether they support any extensions, such as SSE, it is understandable that they, unlike stream processors inside graphics processing engines, can perform complex operations and even run operating systems (hence, we can make a conclusion that chip level virtualization is in place).
Theoretically, the 48-core chip could even process graphics using ray-tracing method or even using traditional fixed-function pipeline if it was equipped with appropriate units. However, even if it has been equipped with GPU-specific blocks, it would have performed slower than conventional graphics processing units with up to 1600 stream processors.
One thing regarding SCC is clear: the future processors will feature tremendous amounts of cores and the general architecture of chips will be different compared to the existing microprocessors.