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As another important improvement in NAND flash, the supply voltage is going to be reduced from 3.3 to 1.8 volts. This will coincide with the introduction of the first-generation DDR flash (133 Mbps). And the next step will be to increase the number of allowable erase/write cycles in enterprise MLC memory. Today’s MLC flash memory type supports 3000 rewrite cycles whereas early commercial versions of eMLC increase this value to 6000 (in the new enterprise SSDs from Intel). The developers even promise to improve eMLC to 30,000 rewrite cycles in the future.

To understand the ways for SSDs to improve, we can take a look at the data from Qualcomm showing the changes in the basic specs of flash memory.

Currently, the leading manufacturers including Intel, Micron, Samsung, Elpida, Hynix and Toshiba are preparing to switch from 30nm to 20nm tech process for NAND flash. Alas, the smaller tech process will worsen the consumer properties of flash memory cells. The service life is reduced from 3000 to 2000 or an even lower number of rewrites (we are talking about the MLC memory type here as the other types won’t switch to the 20nm tech process). The charge retention time is going to decrease, too, but not far below 5 years, so that’s unimportant for SSDs which are used on a regular basis.

The size of a data page may remain the same at 8 kilobytes but the manufacturers will hardly be able to keep the raw bit error rate on the same level. As the tech process gets thinner, the interference of adjacent cells grows up, the number of electrons in the floating gate is decreased, and the leakage currents in the slim insulators get higher. All of this calls for more ECC bits and for faster ECC processors. The existing 24 ECC bits for 1 kilobyte of data won’t be sufficient for long. The 20nm generation of chips will have 80 or even more ECC bits per 1 KB of data. Besides, the controller developers suggest adaptive ECC which would be able to occupy memory pages intended for data.

The problems provoked by the increased error rate, lower service life, larger memory page size, and larger MLC cell (3 or even 4 bits) all require more effective ECC units and make the design and operation of the flash memory controller far more sophisticated. Maybe this is why the backward compatibility of future high-speed NAND chips with existing controllers is so important?

The controllers will have to get smarter as the result. For example, some section of a memory chip may be defective. It may be a line or a column or something else. Factory testing doesn’t always reveal such problems whereas a deeper test would be more expensive. SandForce, a manufacturer of flash memory controllers, suggests that future controllers are going to be equipped with a system of fault tolerance. RAID arrays are the best mechanism of fault tolerance available today, so future SSD controllers will have to incorporate on-die elements of RAID architecture.

As another notable improvement in controllers, the internal SRAM and external DRAM buffer are going to be replaced with internal nonvolatile memory (SandForce has already given up an external DRAM buffer in its controllers). The nonvolatile buffer may be based on such perspective flash memory types as resistive ReRAM (the so-called memristor), magnetoresistive memory (MRAM) or phase-change RAM. As opposed to NAND flash, these memory types are considered “eternal”. They are also fast enough to serve as buffer memory. Of course, such a buffer wouldn’t be affected by power failures. In the long-term perspective, not only the buffer but also the whole SSD can be transferred to new memory types such as the mentioned three.

There is also a concept of burning NAND flash cells with variable speed to achieve more flexibility in the operation of SSDs. The concept of adjustable dynamic and static performance allows producing SSDs tailored specifically to different applications. If you need the maximum speed even though the service life is short, you can use static performance. If you need the maximum service life and want the peak speed in some situations only, you can use adjustable dynamic performance.

Thus, the flash memory cells will slow down in noncritical tasks but will offer their best performance when you need it.

Of course, a practical implementation of all these innovations requires some improvements on the software part of the controllers, OSes and host controllers. Today’s computer platforms are HDD-oriented and, as our tests suggest, the developers of RAID controllers and chipsets still have a lot of work to do until SSDs begin to behave predictably. Here is an illustration from Samsung:

The same SSD behaves completely different on different controllers, the variation getting bigger as the request queue depth gets longer.

We’ve mentioned new types of nonvolatile memory above. It must be said that NAND flash and its ecosystem are going to constantly improve, too, in terms of interfaces and tech processes as well as cell depth, packaging and microarchitecture.

Flash memory with 3-bit cells has occupied up to 25% of the NAND flash market in the last 2 years. It was first produced by Toshiba but now the Japanese company has been joined by Samsung and Intel with Micron. By the end of the next year 3-bit-cell memory is going to account for 35% of the market whereas 4-bit-cell memory will take 5% of it.

 

3- and 4-bit-cell flash is supposed to have different applications: memory cards and USB drives, respectively. The higher bit depth of a memory cell makes the controller and ECC much more complex. Although such memory can lower the price of storage, it has lower performance and a lower number of rewrite cycles, but we have no doubt the manufacturers will try to find a compromise between low price and acceptable reliability and will eventually produce SSDs with 3- and 4-bit-cell memory.

 
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