NVIDIA GeForce4 Ti 4800
(NV28)

ATI RADEON 9700 PRO
(R300)

NVIDIA GeForce FX
(NV30)

Manufacturing technology

0.15micron

0.15micron

0.13micron

Number of transistors

67mln

110mln

125mln

Chip frequency

300MHz

325MHz

500MHz

Graphics memory controller

128bit
DDR SDRAM

256bit
DDR SDRAM

128bit
DDR II SDRAM

Graphics memory frequency

650MHz
(325MHz DDR)

620MHz
(310MHz DDR)

1000MHz
(500MHz DDR)

Peak memory bus bandwidth

9.9GB/s

18.9GB/s

15.2GB/s

Max graphics memory size

128MB

256MB

256MB

AGP interface

AGP 3.0 4x/8x

AGP 3.0 4x/8x

AGP 3.0 4x/8x

Pixel pipelines, pixel shaders

Pixel pipelines

4

8

8 [1]

Texturing unites per pipeline

2

1

1 [1]

Max number of textures during multi-texturing

4

8

8

Texture filtering types

bi-linear
anisotropic
tri-linear
tri-linear + anisotropic

bi-linear
anisotropic
tri-linear
tri-linear + anisotropic

bi-linear
anisotropic
tri-linear
tri-linear + anisotropic

Max anisotropy level

8

16

8

Pixel shaders version

v.1.3

v.2.0

v.2.0+

Branching, subroutines and loops

none

none

none

Max number of textures per shader

4

16

16

Max number of texture instructions

4

32

1024

Max number of arithmetic instructions

8

64 (+64) [2]

1024

Max number of instructions per shader

12

96 (+64) [2]

1024 [2]

Registers

2 color registers,
8 constant registers,
4 texture registers,
2 time registers

2 color registers,
32 constant registers,
8 texture coordinates registers,
16 TMU identification registers,
12 time registers,

4 resulting color registers,
1 resulting Z register

2 color registers,
512 (1024) constant registers [3],
8 texture coordinates registers,
16 TMU identification registers,
16 (32) time registers [3],

4 resulting color registers,
1 resulting Z register

Data representation formats
[4]

Fixed point

Fixed point,
16bit floating point,
32bit floating point

Fixed point,
16bit floating point,
32bit floating point

Vertex pipelines, vertex shaders

Vertex pipelines

2

4

3

Vertex shaders version

v.1.1

v.2.0

v.2.0+

Branching, subroutines and loops

none

static

Dynamic

Max number of instructions per shader

128

256

256

Max number of instructions with loops extension

128

65536

65536

Registers

16 input registers,
12 time registers,
96 constant floating-point registers,
1 address register,

8 output registers for texture coordinates,
1 fog color output register,
1 vertex position output register,
1 pixel size output register,
2 output registers for diffuse/mirror color component

16 input registers,
12 time registers,
256 constant floating-point registers,
16 constant integer registers,
16 Boolean registers,
1 address register,
1 loops counter register,

8 output registers for texture coordinates,
1 fog color output register,
1 vertex position output register,
1 pixel size output register,
2 output registers for diffuse/mirror color component

16 input registers,
16 time registers,
256 constant floating-point registers,
256 constant integer registers,
256 Boolean registers,
1 address register,
1 loops counter register,

8 output registers for texture coordinates,
1 fog color output register,
1 vertex position output register,
1 pixel size output register,
2 output registers for diffuse/mirror color component

Data representation formats

32bit floating-point

32bit floating-point

32bit floating-point

Full-screen anti-aliasing

FSAA methods

Supersampling,
Ordered grid multi-sampling
(OGSS, OGMS)

Rotated grid multi-sampling
(RGMS)

Supersampling,
Odered grid multi-sampling
(OGSS, OGMS)

Number of samples

2 (OGSS, OGMS),
Quincunx,
4 (OGSS, OGMS, OGSS+OGMS, only in Direct3D)

2, 4, 6

2 (OGSS, OGMS),
Quincunx,
4 (OGSS, OGMS, OGSS+OGMS – only in Direct3D ),
6 (OGSS+OGMS, only in Direct3D),
8 (OGSS+OGMS, only in Direct3D)

Technologies helping to use the graphics memory bandwidth more efficiently

Hidden Surfaces Removal (HSR)
[5]

yes

yes

Yes

Frame-buffer compression
[6]

none

yes

Yes

Z-buffer compression
[7]

yes

yes

yes