X-Bit Labs: Respect Lost
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Discussion on Article:
DDR2 vs. DDR: Revenge Gained
X-Bit Labs: Respect Lost
Spinzero... it is 'embarrassing' that you can not spell, it is "embarrassing" not embaressing
It is amazing how many replys to the articles on this site are IRONIC!.
In the article are there any spelling errors?. NO, and the title " DDR2 vs. DDR: Revenge Gained" May be 'twisted', yet, is this a better title?
" DDR2 vs. DDR: revenge is best served cold".
Now, do you have anything useful to say concerning the actual content of this article? Any retort for the points that orangfsh made? No? Well, thanks for playing anyway.
queuetrip: Jack-Ass Exposed
I had to do a double take after i started reading it. I thought i must have clicked on a link to a Babblefish translation of some kind. Yikes!
"Some time is always necessary as an adaptation period during which the users are grieving over the good old past and the bad new present while the manufacturers are improving the parameters of their new products."
"It couldn’t but it can now!"
Punctuation - It's a word. Look it up. It is kind of important. Try throwing a comma in there every so often.
"The ASUS P4P800-E Deluxe is among such Socket 748 mainboards."
Ah, yes. The socket 748. Truly a rare but important member of the Intel family.
"The main question we’re going to answer is if the more progressive DDR2 SDRAM can lift the performance level of i915/i925-based systems to that of i875/i865-based computers."
And, if you can get beyond all the wonderful fact-checking and beautiful grammar, this is what we are left with. The discovery of whether or not Intel's latest technology is as fast as the technology they released 2 years ago. Truly, revenge has been gained!
-A few selected quotes from the article
"Whereas current DDR (I) is capable of running at 400 MHz data rate with one penalty cycle each for the Bank Activate (tRCD), the Read (CAS) delay and the Precharge Delay (tRP), that is, at 2:2:2 latency settings, DDR-II will incur three penalty cycles for each of the above mentioned parameters, and run at 4:4:4 at the same operating frequency."
"The numbers just mentioned only hold for Read accesses, on Writes, the situation is slightly worse. DDR (I) writes are executed at CL-1, that is, immediately after a write command is given and without any penalty cycles. In DDR-II, the Write CAS Delay is specified as Read latency minus 1, that is, a CL-4 module will run at a write latency of 3 clocks."
Opinion on seeing AMD giving the Athlon64 a DDR2 memory controller
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