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One of your better written articles, with a lot of good background information to flesh out the current point.
However, additional stages do not mean lower IPC, necessarily, nor do they necessarily allow for higher clock speeds. The perfect example is the Athlon 64 which has additional stages for increased IPC, not for clock speed.
You only reach increased clock speeds when you spend more stages on the same function and remove the bottleneck. So, if I use three cycles instead of two for whatever function, that particular part can run at higher clock speeds, and presuming it was a limiting factor, the processor can.
If I add additional stages that do something that was not being done, or is now being done better, it is not going to add to clock speed. I bring this up because my suspicion is that Intel may have added a stage or more for scheduling or stages that are in some way related to feeding the extra integer pipeline. I could very easily be wrong, but when you figure that AMD doesn't know how to do this, and Intel didn't with the Pentium III and Pentium 4, it could be they need an extra stage or two to help with scheduling instructions so the extra pipeline is actually utilized sometimes. Again, just speculation, but what isn't speculation is that the extra stages in the A64 were for IPC and not extra clock speed. So, it's a bad oversimplification to make that assumption. It might be better to say that generally longer pipelines lower IPC and increase clock speeds, but not in all instances.
One last point, the Pentium III had a longer pipeline than the Athlon, but couldn't hit the same clock speeds. So, as a generality, OK, but anything more than that is disinformation.
However, additional stages do not mean lower IPC, necessarily, nor do they necessarily allow for higher clock speeds. The perfect example is the Athlon 64 which has additional stages for increased IPC, not for clock speed.
You only reach increased clock speeds when you spend more stages on the same function and remove the bottleneck. So, if I use three cycles instead of two for whatever function, that particular part can run at higher clock speeds, and presuming it was a limiting factor, the processor can.
If I add additional stages that do something that was not being done, or is now being done better, it is not going to add to clock speed. I bring this up because my suspicion is that Intel may have added a stage or more for scheduling or stages that are in some way related to feeding the extra integer pipeline. I could very easily be wrong, but when you figure that AMD doesn't know how to do this, and Intel didn't with the Pentium III and Pentium 4, it could be they need an extra stage or two to help with scheduling instructions so the extra pipeline is actually utilized sometimes. Again, just speculation, but what isn't speculation is that the extra stages in the A64 were for IPC and not extra clock speed. So, it's a bad oversimplification to make that assumption. It might be better to say that generally longer pipelines lower IPC and increase clock speeds, but not in all instances.
One last point, the Pentium III had a longer pipeline than the Athlon, but couldn't hit the same clock speeds. So, as a generality, OK, but anything more than that is disinformation.
[Posted by: TA152H | Date: 02/10/06 01:54:00 PM]
