4.
In this article and the first you seem to suggest that HyperTransport is capable of 8GB/s peak bandwidth, which if actually available, would allow DMA transfers from memory to approximately match the dual PCI-E x16 total of 8.2GB/s.
In the first article you actually stated 16GB/s combined bandwidth for Hypertransport but this is not true! The current fastest HT clocking is 1000MHZ with DDR for 2GT/s, with a data width of 16-bits, for a rate of 4GB/s. This is, of course in each direction, so the combined (up & down) max is 8GB/s.
With a max available bandwidth path of 4GB/s between memory and the chipset, it's hardly surprising that there is no significant improvement in performance with SLI x16.
In fact I suspect that this HT limitation could be the reason for the significantly faster Intel Dual Core game benchmarks published by Anand et.al. IOW Intel has jacked up the internal clock multiplier in the i975x chipset used for those benchmarks... or the internal data width was increased, something which Intel does not publish in its datasheets.
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Posted by: LairdDramBeg

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Date: 03/12/06 10:37:53 PM]