Duh. its called speculative execution. Go read up bud.

Your piece of code means that you have no idea how CPUs work. You probably have a computer science degree but not a computer/electrical engineering degree.

CPUs are far more complicated than that and your code proves nothing.

Time will tell if this reverse thingy worth it or not.
I believe it will be a big hit if this news story is correct.

A core has multiple FPU units because it can process multiple instructions in parallel (and out of order).
The thing is, it happens on one core, meaning the instructions all share the same register file and the same OOO logic. That means one instruction can be assigned to either one of the FPU units with no penalty.

However, doing the same between cores is a radically different thing. At the very minimum, you need to transfer the instructions to the other core, and transfer the resulting register changes back to the first core. Then you need the logic to keep track of which instructions are currently being processed on the other core, as well as when you can expect to see the result. This is already being done inside each individual core, where latency isn't a factor.

The key point here is that it is only an advantage if you can find instructions that are independent, and assign them to a FPU unit each. However, independent instructions are hard to come by. Sooner or later, the result *will* be needed, which means you get a dependence. If the result you need is residing on a different core, you have to wait *a long* time for it to get back to you. That means *lower* efficiency, not higher.

If you have multiple threads, this works fine, because the two cores do not attempt to interleave or mix instruction. Each core is assigned one thread exclusively, and so, it doesn't matter how long it'd take to get a result from instructions processed on the other core.

Splitting a thread across multiple cores is different, because you constantly need access to previously processed instructions, to act as input for new ones. That's ok on single cores with multiple FPU units, because they're all close to the register file, so their results can be returned quickly. But having to send it across a hypertransport link from core A to core B would introduce a delay that'd really hurt performance.

Actually you got it wrong. For a programmer this makes sense, but for an engineer it doesn't.

Actually it may be good idea. At least with K8 architecture. Remember that both cores communicate with each other via some 'direct-connect-request-bus' and memory controler is there too. IMHO it is only matter of adding more logic to this part and make it more like Ati thread dispatch arbiter. There will be latency, no doubt, but using twice resources may finally increase performance about 50% in single-threaded appl.

Excuse my english. Im not native.

Intel = Idiots 'n' terribly empowered lammers :D
Nice flame.