1.
About the changing of the way we overclock, it is true that one can't OC any more a SB processor the way we used to. There are two things though that I'd like to point out:
1.$$$-aware customers and low cost OCers didn't really considered Intel as a real option, except in the brief Celeron 300A days and a bit in the C2D-based Pentium DC days. What is lost now is competition in the 100 to 200$ market for offering the best OCing chip. Intel practically set a great pass to AMD, now AMD has to touch-down with Bulldozer.
2.In the 2000's PCI clocks were tied to FSB, thus overclocking was difficult as they are now in SB. We could have gained most 10% without PCI/AGP lock. Now there are many more components integrated on the boards, which have higher speed and thus are more sensitive - the result is only 1-2% bclk is possible in SB. Intel can introduce a second PLL on-board to take care of all the rest clocks except bclk and recycle a synchronization protocol between these two clocks from the FSB-era chipsets. They haven't implemented that in SB probably because of the complexity of the new architecture. If they're gonna do it or not in Ivy Bridge, it depends on how much mind-share they're gonna loose with enthusiasts due to the solution adopted in SB.
1.$$$-aware customers and low cost OCers didn't really considered Intel as a real option, except in the brief Celeron 300A days and a bit in the C2D-based Pentium DC days. What is lost now is competition in the 100 to 200$ market for offering the best OCing chip. Intel practically set a great pass to AMD, now AMD has to touch-down with Bulldozer.
2.In the 2000's PCI clocks were tied to FSB, thus overclocking was difficult as they are now in SB. We could have gained most 10% without PCI/AGP lock. Now there are many more components integrated on the boards, which have higher speed and thus are more sensitive - the result is only 1-2% bclk is possible in SB. Intel can introduce a second PLL on-board to take care of all the rest clocks except bclk and recycle a synchronization protocol between these two clocks from the FSB-era chipsets. They haven't implemented that in SB probably because of the complexity of the new architecture. If they're gonna do it or not in Ivy Bridge, it depends on how much mind-share they're gonna loose with enthusiasts due to the solution adopted in SB.



| Date: 01/04/11 01:36:27 AM]
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| Date: 01/08/11 03:20:01 AM]
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| Date: 01/28/11 12:52:12 AM]

