The SIMD processing area was already split in the Cypress. The link you gave me does not say it's VLIW5. All it says is that the two split areas now have their own dispatch processor, instructor and constant caches. The parallelism is increased, but in theory it should only yield about 3% in overall performance with todays' games in general. This does not account for the nearly 20% increase that only makes sense with the VLIW4 architecture.

Barts LE with its sawed-off 16 ROPs might still have 256-bit memory traces on the PCB, but only be able to access 128-bit per given cycle since the ROPs are linked to the bus. Thus, it's more appropriate to call it 128-bit like AMD did with their HD 4730's. The first link that I gave you above should cover quite a bit.