I don't think what you said is entirely inaccurate, it probably will be similar performance to llano, but with a few caveats.

With in essence 160 shader processors, and a clock similar to Ivy bridge (1150-1300mhz), it could more-or-less match the lower-end Trinity (256sp @ 760mhz) in compute (or llano, 400 at 600mhz since 5D is generally less efficient) given the disparity of power efficient clocks between 22nm and 32nm (at probably around 1.05v).

That said, the native design seems geared toward having enough bandwidth, unlike trinity that may very well choke with 384sp versions. While AMD's design decisions may come down to toss-ups between getting decent yields and having an upper-end part that can use all bandwidth of the cpu when a task is completely devoted to the gpu, Intel's structure looks to be very efficient for what it is: a practical inherent resource split of an igp within a cpu tdp.

None of them have made the perfect omelet, but design, yield, and power realities kind of disrupt that from being practical.

I agree it's pretty much a race to whom can get enough shaders to saturate the equivalent of 4 ROPs (probably around 1.5-2x the gpu core logic haswell will have) at an energy efficient clock for the given process, supplying enough bandwidth to make it practical, having a strong-enough cpu for general tasks, while living inside realistic tdps for each given market.

AMD and Intel are both headed in that direction, but from opposite strongholds. Much of why it hasn't happened yet can probably be attributed to Intel's manufacturing lead (process and quality) re: AMD (which will probably get there on a smaller node) mixed with Intel's inexperience in creating appropriate consumer graphics architectures (causing them to rely on a stronger cpu which innovation has typically been their strong suit).