Not true. You need to distinguish how power-efficient the A15 and Krait microarchitectures can be, as opposed to how efficient the current generation of tablet-optimized SoCs are making them.
The chips that you cite are optimized for tablets and are running the CPU at high clocks/voltages. In addition, the current S4 parts are on TSMC's 28 nm LP process, which is not their lowest leakage/power variant (at least not any more).
Samsung is less public about their process technologies, but based on clockspeed it appears that the chip used in the Chromebook was optimized for speed rather than for power. It is instructive to observe how Apple is able to fab both their regular (A5, A6, etc) and "X-series" (A5X, A6X) SoCs (system on chip) on the same Samsung process family. The part you cite in the Chromebook is the equivalent of an Apple X-series SoC.
It should be possible to get the A15 down within a much lower power envelope by reducing clockspeed and voltage, and by using a lower-leakage process variant like TSMCs 28-HPL (High-K, low-power).
Note in particular that:
1. Non-leakage power goes as clock speed times voltage
2. Max clockspeed is ~linear with voltage
This means that reducing clockspeed by ~30% reduces non-leakage power by ~50%. Couple that with a lower-leakage high-K process and you could easily cut overall power in half.
I'm personally not a huge fan of the ARM architecture, but one must be fair/honest about these things...
11/18/12 01:16:55 PM]