Wow. This guy hits and he misses. There is some good supposition here, but there is also blatant error. He has no idea about DDR2 technology, and thus some of his conclusions are based on false premises. Not bad, but I'd say he's only about 50% right.

what will happen if rambus wins infringement suits and ddr2 also has same royalties (or more likely) than xdr ??? this is a reasonably likely event don't you think ?

Addition to 1. - It's not only about DDR2 - I discovered some other false belief, while quickly glancing over the article:

Although complex operations on 64bit integer data (like multiplication and division) are slower* than on 32bit, this is not the case for majority of instructions - the most used ones are amongst them, like MOV, LEA, ADD/SUB, boolean operations, shift/rotate etc. So we would only loose a few percent performance if we completely change 32bit code to 64bit. And for things, which are better done in 64bit or even more (think about crypto stuff, fast string searches in databases etc.), the 64bit code will clearly win against 32bit code even with slower mul instruction (because 64bit multiplications using 32bit are much slower).

But: it's not necessary to use 64bit values. If 32bit are enough, they work as fine in 64bit mode as they do in 32bit modes.

And: the (not mentioned) additional registers (GPRs and SSE2) offer increased performance even for 32bit code.

Never forget: The additional address space and wider registers are not the only benefits.

*) MUL: 1/2 throughput, 2/3 higher latency vs 32bit, DIV needs about twice the time

Hmmm

AMD has two potential aces up its sleeve:

1. They are most likely working on coherent HT technology that will obviate the need for a proprietary interconnect. This will commoditize the big iron market completely.

2. Longhorn has trusted computing built into the core, and TC needs special support in the processor, which AMD already has built in (IMHO). Microsoft is working very closely with AMD in this respect, and they will beat Intel to market.

Intel has got a serious problem, after f*cking around with the Itanium for so long.

How can two K8s on one chip share the L2 since it is inclusive L2 cache? They'd also need to share the L1...

Why would you have to buy a dual chip license? With the hyperthreading you have one chip that looks like two cores. Why would it be different for AMD CPUs just because when using both cores they don't run at half speed. The only justification I can see for charging for two would be if it looks like two CPUs from the BIOS-if there was no difference between a dual core chip and a pair of Opteron 2xx chips. I doubt that will be the case.

"Thus, we can integrate two processors into one die and the resulting chip would be about 200 sq. mm"

Why should dual cps have the double size of one? Two caches, Two memory controlers, Two xxx..... must every thing be replicated?
If it's like you are saying beside saving space, where is the need of making two cores in one chip? Two chips with one core already do. Where is the price/wise of making such chip?

Why doesn't ati integrate two 9600 cores in one chip, instead of making 9800 chips? You are all wrong about dual core chips!

IBM have one? I didnt know? How does it work?

I have had a few thoughts about the K9 since reading your opinion.
The implimentation of DDR2 and HyperTransport2 are highly likely, but what about the core? Dual core is all the talk, and both AMD and Intel are know to be developing such CPU's, but is there the possibility of something else?
I have read speculation that there will be 15 stage integer pipeline (maybe) and there has been comments about Hyperthreading by at least one AMD exec, that it could make sense if you think of a much wider core. When you think about a dual cored K8 you have 6 integer pipes plus there address units (each core has 1 complex integer unit and 2 simple ones) and 6 floating point pipes (that can also process 1 128bit sse1&2 intruction (128bit split in 2 and run down 2 of the pipes)). One could ask what advantage would a hypertreaded core have over a dual core? Well imagine this. With 5 integer pipes, 2 complex (each reserved for seperate threads) and 3 simple pipes that are share by both threads, you could have the same performance as the dual cores, because hypertreading will compensate for the pipeline "bubbles" that are present in all processor designs. The transistors saved can be spent else where. Having 6 floating point pipes would probably give the same performance as a dual core, BUT remember that floating point pipelines do dual function. With a dual core you could only double your sse1&2 performance, but with 6 pipes in the 1 core, it could be possible to TRIPLE your performane with these instructions. Imaging the multimedia and scientific calculation performance (as these uses leverage sse1&2 the most) from such as design. Now it is quite possible that I have read too much into all the little snippets of information that is out there, but what a way to go?!

Isn't DDR2 twice as fast as normal DDR1 memory at the same speed? I recall reading that in a detailed article about DDR2.

Anyway the future of AMD looks very bright.

The L2 is exclusive - no problem then.

To K9:
Go to http://www.uspto.gov/patft/index.html and look for AMD patents (advanced search, enter there: an/"Advanced Micro Devices" ).
http://www.chip-architect.com/news/2001_10_02_Hammer_micro architecture.html has some interesting patent numbers too.

K9 might have (speculation according to processor architectures shown in the patents) 16 functional units and 6 decoders, an L0 instruction cache (256 or 512 bytes, fully associative). The units are grouped into 2 sub-cores (that means for example: still only one L1 I and D cache).

What are you talking about DDR2? It's obvious that it is slower. Today I've read TheInquirer, and it told that DDR2 will cost alot, but deliver poor performance. The author of this article is absolutely right. Or am I missunderstanding something?

I believe that the suppositions that were proposed in this article hold the utter most truths within as the proof that was followed by them completely backed up all statements made. An exception may occur in the last page or so though, but highly likely!

AMD doesn't definitely have problems with strained silicon process (later SSP), or process itself is not anyway problematic. AMD has been co-operating with IBM in development of SSP. It's well known and documented that Intel (Prescott) has current leakage problem, whilst PPC970FX doesn't have. IBM does their PPC970FX processors with SSP and allthough yields are low yet, at least they really work and have potential, unlike Prescotts.

Since AMD has same knowledge about strained silicon process as IBM, they should also be able to implement it correctly (while Intel can't do yet). Problems with mfg. plant (Dresden or whatever) are of course different problem, but everyone has 'em.

If it's severe problem with plant, AMD could buy needed high-specs units from IBM, since it's already using 0.9micron SSP in East Fishkill, which has spare capasity. East Fishkill is also supposed to produce dies for other manufacturers than IBM.

philosipher's stone? somebody been watching cartoons