Bulldozer x86 architecture

Approaches for supporting multiple threads

Bulldozer concept

Bulldozer

Core microarchitecture - Shared frontend

Core microarchitecture - Dedicated cores

Core microarchitecture - Shared FPU

Core microarchitecture - Shared L2

Prediction - Directed instruction prefetch

Multiple data prefetchers

New Floating-point instructions

Thread control and selection mechanisms

Bulldozer ISA and feature extensions

Power efficency and APM

Concluding remarks

The Northbridge

SRQ, Crossbar, Memory controller

DRAM controllers, L3 cache, Probe Filter

Four 16-bit HyperTransport links

Power Management

Core C6 State (CC6)

P-states, AMD Turbo Core

Turbo Core