IBM already offers its dual-core Power4 processors able to work with two threads in total. Next year IBM unveils its Power5 dual-core chip capable to handle up to four threads simultaneously. IBM expects from the Power5 up to four-fold performance boost due to new and more efficient architecture over the previous generation of server CPUs. IBM is currently fully satisfied with the test results of preliminary sample of the Power5 chip made using 0.13 micron technology in its laboratories. The CPU will initially run at 1.50GHz.
Sun Microsystems intends to roll-out its dual-core, UltraSparc IV chip able to handle two threads this year. Even later, sometime in 2005, the company plans to launch its H series of server processors. One H processor is based on eight modified UltraSparc II cores, each capable of executing up to four threads simultaneously, providing ultimate power and being able to handle up to 32 threads.
I wonder how many megabytes of cache such multi-core, multi-thread monsters will require. IBM claims that its special data-transfer methods between regions of main-memory will be implemented in the Power5-based systems, though, IBM does not indicate if it is enough. Since large on-die caches often occupy a lot of transistors, MPUs with huge caches cost tens of thousands of US dollars.
Intel’s code-named Montecito IA64 processor will be made using 90nm manufacturing technology and will be out in 2005. It will feature 18MB of L3 cache and clock-rates well above 1.50GHz.