Besides some facts about AMD’s next-generation project code-named K9, the company’s CTO Fred Weber also disclosed a number of details concerning forthcoming CPU micro-architectural innovations at his keynote at Microprocessor Forum 2003.
In general, the key peculiarities of future microprocessors reflect not only AMD’s vision of further CPU development, but also contain a number of approaches other chip companies plan to deploy. It is very interesting to note that these innovations are agnostic to CPU instruction set; e.g. such measures of performance boosting will be engaged by virtually all microprocessor families, such as x86, PowerPC, EPIC, ARM, SPARC and so on.
According to AMD’s Fred Weber, the paramount forces to be deployed by the next-generation chips, such as AMD K9, AMD K10, etc are as follows:
- Threaded architectures;
- Chip level multiprocessing;
- Huge scale MP machines;
- 10GHz operation;
- Much higher performance superscalar, out of order CPU core;
- Huge caches;
- Media/vector processing extensions;
- Branch and memory hints;
- GHz performance IO;
- Security and virtualization;
- Static and dynamic power management.
In fact, there is nothing really new in those patterns and some of them are either already available, or are just around the corner.
For instance, we do already have multi-threaded architectures, such as Intel’s Hyper-Threading, in the market, we are probably going to see more innovations in this field from Sun, IBM and AMD. I would even expect some multi-threading to emerge in the K9 design, but since the chip is quite far from here, we cannot state anything for sure.
Chip level multiprocessing is planned to be available in high-end IBM’s Power5 processors next year, while Sun, Intel and AMD plan to debut with their dual-core chips in 2005. In respect of AMD, its first dual-core chips will be based on K8 architecture, according to the company. Intel will also introduce dual-core Xeon and Itanium processors in future.
Operation at unbelievable frequencies, huge caches as well as powerful CPU and I/O buses are inevitable parts of performance progress. There are no doubts that AMD K9, AMD K10, AMD K11 in addition to other microprocessors will work at high core-speeds and employ large L1, L2 and possibly L3 caches. Obviously, the K9 will hardly achieve 10GHz, but K10 will surely hit this important milestone. It will be amazing in case after 10GHz we will see 20GHz, 30GHz and so on, just like we witnessed the thorny way from 10MHz to 33MHz in the eighties.
Other innovations, such as media and vector processing extensions, branch and memory hints and so on, are also found in the majority of today’s CPUs starting from Pentium Pro, Pentium MMX and AMD K6-2 3DNow!. Expect more extensions of such kind in AMD’s Athlon 64 processors as well as K9 and K10 chips.
We already know from our previous reports that AMD K9 will support Palladium security capabilities from Microsoft, the presentation probably confirms this previous statement.
Finally, it is very interesting to hear about dynamic power management in desktop processors. So far there have been only static kinds of power management, while dynamic was a prerogative of mobile processors. Looks like we are going to have the feature enabled in desktop CPUs as well.
To sum up, the way from 5MHz to 3200MHz was exciting and took 25 years. Will there be a complicated way from 3.20GHz to 2048GHz in Intel’s and AMD’s projects during the next two and a half decades implementing the principles claimed by AMD and Intel executives nowadays?