The Inquirer has managed to picture IBM’s upcoming POWER5 chip featuring 4 chips with 8 cores and staggering 144MB of total cache during the presentation of the CPU at Microprocessor Forum 2003 in San Jose, California. As revealed earlier this year, the POWER5 is healthy going from tape-out to mass production in 2004, now you can see the proof here. 

Each IBM’s POWER5 chip contains two cores sharing 1.92MB of L2 cache and 36MB L3 cache. POWER5 typical processor is a 95mm x 95mm MCM with 4 chips (each chip contains 2 cores) feature astonishing 144MB of cache memory. POWER5 feature on chip memory controller that can address up to 1024GB of RAM. IBM says up to 16 MCMs may be combined in one logical system to built a monstrous server solution with 128 powerful CPUs. Core-clocks of POWER5 will be about 2.0GHz at launch in 1H 2004.

Software originally developed for POWER4 64-bit processors will be compatible with the POWER5.