X-bit labs

AMD Dual-Core Opteron Processors to Feature 940-pin Packaging?

Category: CPU

by Anton Shilov

[ 11/28/2003 | 03:10 PM ]

Advanced Micro Devices may have great headroom with its Socket 940 Opteron processors for servers and workstations, as there are claims about dual-core chips made using 90nm fabrication process in 940-pin packaging.

 “AMD does not exclude a possibility to launch 90nm dual-core microprocessors in 940-pin packaging,” a person with good knowledge of Sunnyvale, California-based CPU maker plans said.

AMD’s officials made it clear this September that the first dual-core AMD Opteron processors featuring AMD64 aka x86-64 technology would be manufactured using 90nm SOI technology. In late 2005 AMD plans to start transition to 65nm fabrication process trying to deploy the manufacturing lines of its upcoming Fab 36 in Dresden, Germany; therefore, we may be nearly confident the first dual-core chips by AMD will be manufactured using 90nm design before the year 2006. Furthermore, the timeframe for chips with two times more power compared to conventional microprocessors may be in-line with Intel’s schedule for such products – the second half of 2005.

940-pin packaging does not necessarily mean that those dual-core CPUs from AMD will be compatible with existing architecture. Following the Athlon 64 roadmap, I reckon that at least some of next-year’s AMD Athlon 64 FX processors for desktop application will function using faster 1000MHz HyperTransport bus, a 200MHz increase over current 800MHz HyperTransport links used by such CPUs. There are informal indications about Socket 754 microprocessors with 1000MHz HT bus effectively meaning their possible incompatibility with existing Socket 754 infrastructure.

In case AMD’s dual-core Opteron microprocessors also have faster HyperTransport bus, they will require a new platform. Nevertheless, if those chips use 800MHz HT, there will be probably a great upgrade opportunity for AMD Opteron servers.

Intel’s dual-core chip currently known as Tulsa will emerge in about two year’s time – its roadmap is aligned with Intel’s dual-core IA64 chip code-named Montecito. This will be the first Xeon and also the first IA32 microprocessor with two cores. Thanks to the Hyper-Threading technology, the chip will be able to handle four or more threads at once, competing with solutions from other server chipmakers. There is no information about infrastructure for Intel Xeon “Tulsa” at the moment.

Two processing cores is a great way to improve performance of microprocessors at a more or less affordable price-point. At present, Xeon MP-based computers have only one dual-channel memory controller for all microprocessors in the server, as a consequence, up to 4 chips tend to utilise one memory bus with limited bandwidth. In case of dual-core design, the same kind of bottleneck may emerge on AMD Opteron successors in 940-pin packaging that will obviously have dual-channel memory controller for both cores. The issue will not be as dramatic, as with current Xeon MP platforms, frankly speaking.

Official representatives from AMD did not comment on the story.