At the 2003 IEEE International Electron Devices Meeting (IEDM) in Washington, DC, AMD provided additional detail on its next-generation silicon-on-insulator (SOI) transistor design, while also providing new information on its successful use of SOI technologies in its current microprocessors.

AMD’s new 45nm transistor is expected to offer a high-confidence solution to many of the most critical challenges the semiconductor industry expects to face at the 45nm technology generation, according to AMD.

Currently, the International Technology Roadmap for Semiconductors forecasts that transistor gates, the primary parts of transistors that turn the flow of electricity on and off, will need to be as small as 20nm in order to achieve performance projections for the 45nm generation. Today, minimum gate lengths in the highest-performance microprocessors from AMD are approximately 50nm, AMD said, but did not elaborate which of its chips it points out.

AMD’s new transistor design uses three gates, instead of one as in today’s transistors, and incorporates several innovations that allow for continued transistor gate scaling down to 20nm and below, while providing increased speed and decreased electrical leakage. Further, AMD’s transistor is not dependent upon the use of so-called “high-k” gate dielectric materials, which have been shown to have negative effects on some aspects of transistor performance.

AMD research technologies used in the new multi-gate design include:

• Fully depleted SOI: The next generation of silicon-on-insulator (SOI) technology that increases the performance and power-saving benefits of today’s SOI.
• Metal gates: Gates made from nickel-silicide, rather than polysilicon as they are today, in order to improve electrical flow while reducing unwanted leakage.
• Locally strained channel: A revolutionary way of combining advanced materials in a geometry that naturally “strains” the atoms within the transistor’s electrical path so electricity can flow more fully.

AMD’s next-generation SOI research builds upon the company’s current products using SOI in a high-volume manufacturing environment within AMD Fab 30

AMD also provided information for the first time on its leadership in introducing what are known as “low-k” dielectric materials for improved circuit performance. These low-k materials are used to insulate the copper interconnect lines that conduct electrical signals across the chip and reduce the energy that is needed to propagate these signals. AMD was a leader in the introduction of low-k materials into a high-volume manufacturing environment, starting with its 130 nm process in AMD Fab 30.