X-bit labs

Intel to Put More Cache into Xeon DP Processors.

Category: CPU

by Anton Shilov

[ 04/19/2004 | 03:28 PM ]

Intel postponed the release of the new generation Xeon DP processors with Nocona core, but is readying a revamped version of the chip with 2MB of L2 cache in order to significantly boost performance without increasing clock-speed much and not use the brute force of the Jayhawk processor.

Sources close to Intel told X-bit labs there is a special version of Intel’s Nocona Xeon processor with 2MB of level-two cache in the works. Intel Nocona is the code-name for the company’s Xeon processor designed for 2-way servers and workstation with 1MB of L2 cache as well as 64-bit capability. Previously it was said that Nocona will live on for about a year and will be replaced by Jayhawk – a yet another core that is also expected to have 1MB or larger L2 cache. In case the information is correct, Irwindale processor – Nocona’s brother with 2MB L2 cache – will see the light of the day in the Q1 2005 being clocked at 3.80GHz.

The main difference between today’s Xeon processors and Xeon “Nocona” now scheduled for Q3 2004 release is support for 64-bit extension technology; however, there are numerous factors that are likely drive speed of the new Xeon products upwards. Firstly, Nocona’s L1 cache is two times larger compared to the current Xeon DP processors’ and equals to 16KB. Secondly, Nocona includes 16K uOps Trace Cache, a substantial improvement over current 12K uOps. Thirdly, 90nm DP products will make use of Prescott’s new, more efficient branch prediction mechanism. Fourthly, the new Xeon 1M microprocessors will feature SSE3 technology. Fifthly, the new Xeon chips will have 1MB of L2 cache compared to 512KB L2 cache on current offerings. Finally, the new Intel LV Xeon “Nocona” will boast with enhanced efficiency of the Hyper-Threading technology. Additionally, the new Xeon products will operate using 800MHz processor system bus. Unfortunately, Nocona as well as Irwindale is likely to inherit the main drawback of Prescott – exceptionally high power consumption.

Originally planned for the launch in the second half of 2004, Xeon processors “Jayhawk” – successors of Intel Xeon “Nocona” CPUs, are now said to launch in the second quarter of 2005. The Jayhawk core boasts the same micro-architecture as desktop chip code-named Tejas that will continue quantitative and qualitative boosts of NetBurst specifications. The chip will have 24KB L1 cache, 16K uOps Trace Cache, 1MB L2 cache [probably 2MB for 65nm version], a more efficient branch prediction mechanism, a new set of instructions known as “Tejas New Instructions” as well as improved Hyper-Threading organization, according to currently available information.

The main idea of Tejas and Jayhawk processors may not be only rapid performance improvements, but addressing certain problems Intel’s first 90nm chip Pentium 4 “Prescott” ran into, primarily too high power consumption. Resolving thermal issues is likely to ensure that the second generation of Intel’s 90nm CPUs will have more frequency and performance headroom, if Intel succeeds in tackling with the problems, of course.

All Intel’s upcoming Xeon processors with 800MHz processor system bus and Extended Memory 64 Technology (EM64T) – Nocona, Irwindale and Jayhawk – are likely to be drop-in compatible with Intel’s Tumwater and Lindenhurst chipsets. Sources said all the chips use 604-pin packaging.

To successfully compete with rivaling AMD in the field of expensive processors for desktop computers, Intel today offers Pentium 4 Extreme Edition chips with 2MB L3 cache for those who demand some extra power. Such microprocessors are based on 130nm server cores named Gallatin originally developed for MP servers. Since scalability of 130nm process technology is limited to about three and a half gigahertz, no more Extreme Edition processors based on current core are expected to be released, but once Intel has a core produced using 90nm process technology with large cache and greater clock-speed scalability, it may use it for future Extreme Edition processors.

Irwindale is not a flavour of Intel’s future incarnation of Xeon MP product code-named Potomac, sources noted. Potomac will have 1MB of L2 cache and 2MB of larger L3 cache. Irwindale is expected to have large level-two cache and no level-three cache.

There are no official comments on this report.