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Despite of earlier news, Intel’s new high-end 64-bit chip for servers is on-track for Q3 2004 introduction. As expected, a new flavour of Itanium 2 processors with 9MB L3 cache will be introduced in mid-year.

Apparently, there will be two versions of Itanium 2 “Madison 9M” processors with 400MHz and 667MHz processor system bus scheduled for Q3 2004 and Q1 2005 introduction. There is no delay with new Itanium 2 product introductions, it transpires. The IA64 microprocessor with up to 9MB of level-three cache is engineered for high-end 64-bit multi-processor applications.

Nowadays high-end Itanium 2 lineup from Intel includes 1.50GHz, 1.40GHz and 1.30GHz models with 6MB, 4MB and 3MB L3 cache respectively. All the current chips use 400MHz Quad Pumped Bus, 667MHz PSB to be introduced early next year will be the first bump for MP Itanium’s bus speed that is likely to give a strong boost for performance of IA64 MP servers. However, even earlier Intel is expected to boost the PSB clock-rate of Itanium 2 processors designed for 2P servers: in Q4 2004 a cut-down flavour of Madison 9M, chip code-named Fanwood, will get a 533MHz Quad Pumped Bus.

667MHz will be a magic number for Intel processors designed for multi-processor servers. The company’s next-generation Xeon MP processors with Enhanced Memory 64 Technology code-named Potomac will also sport 667MHz processor system bus. The company recently confirmed plans to unify Itanium and Xeon platforms so that both processors would fit into one socket. But the chipmaker does not indicate when exactly this happens.

Official representatives from Intel did not comment on the news-story.

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