X-bit labs

Intel Demos Dual-Core Itanium 2 Processors.

Category: CPU

by Anton Shilov

[ 06/19/2004 | 06:13 PM ]

Intel Corporation showcased a wafer with dual-core Intel Itanium 2 “Montecito” dies at an event in Japan recently. The demonstration reiterates Intel’s commitment to the IA64 architecture and indicates that the company is on-track to mass produce dual-core 64-bit chips next year.

Dual-Core, DDR2, PCI Express Ahead

Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future. Millington is a cheaper version of Montecito, probably tailored to serve 2P systems and contain less cache, LV Millington will have lower power consumption compared to the default core.

An Intel rep holding a "Montecito" wafer.
Picture from Enterprise Watch web-site.

The Montecito and Millington chips will contain a couple of promising technologies: Foxton for dynamic power management and Pellston for correcting data errors in the cache. Intel’s president and COO Paul Otellini recently said that the Foxton is a technology to dynamically boost speed of Itanium 2 chips, but he did not outline, whether this applies to dynamic overclocking or dynamic underclocking. Typically, overclocking is not accepted in mission-critical environments, at the same time, dynamic underclocking can help to reduce power consumption and consequently the cost of ownership.

Intel’s Itanium 2 chips with two processing engine will work using 667MHz Quad Pumped Bus and will feature Intel’s new core-logic for high-end servers code-named Bayshore. The latter is expected to provide support for DDR2 memory and PCI Express interconnection, bringing the latest innovations into the server market.

First Wafers Showcased

As expected, Intel will produce the Montecito using its 90nm fabrication technology utilizing 300mm wafers. The company demonstrated the first wafers with dual-core Itanium 2 dies, indicating that the prototypes had been manufactured and now Intel may even test the actual dual-core microprocessors.

A 300mm "Montecito" wafer.
Picture from Enterprise Watch web-site.

Each dual-core Itanium 2 “Montecito” with 24MB of cache is expected to contain about 1.7 billion of transistors, about 13 times more than modern Intel Pentium 4 chips include.

Madison Gets Speed Boost, Multi-Core Chips in Long-Term

Shortly Intel is projected to release a faster version of its current incarnation of the Itanium 2 processors – the product code-named Madison – later this quarter. Intel Itanium 2 processors with Madison 9M core are designed for powerful multiprocessor servers and will be available at 1.70GHz, 1.60GHz and 1.50GHz with 9MB, 6MB and 4MB L3 cache respectively. Intel also has plans to roll-out cut-down version of Madison 9M – code-named Fanwood – for dual-processor servers and workstation. Both Fanwood and Madison 9M will use 400MHz processor system bus and will be drop-in compatible with existing infrastructure, sources said. Additionally, the chip giant will introduce new versions of its low-voltage EPIC microprocessors also this quarter.

In the longer term Intel gears toward processors that contain more than two cores. The first of the company’s multi-core IA64 processors is code-named Tukwila (formerly Tanglewood). Eventually, there will also be a chip code-named Dimona, a yet another multi-core offspring of the Itanium 2. Both are anticipated for release in 2006 and later.