Advanced Micro Devices recently updated its public roadmap located on its web-site showing that despite of the lack of any global announcements the company ships or shortly plans to start supplies of 90nm chips for desktop, mobile and server segments and will release more 90nm chips during the first half of the year. Additionally, the company confirmed dual-core desktop and server central processing units in 2005, but released no information in regards dual-core mobile products.

Future Plans Showcase More in Present

The new roadmap continues pretty conservative policy of Sunnyvale, California-based Advanced Micro Devices, who is very reluctant to reveal any substantial details about its short-term and long-term future products these days. Apparently, the company aims to start shipping its AMD Opteron 100-, 200- and 800-series processors (code-named Venus, Troy, Athens respectively) made using 90nm SOI process technology before 2004 ends. Besides, the firm also supplies Mobile Athlon 64 and Sempron chips along with Athlon 64 central processing units at 90nm in volume today. AMD issued a press-release claiming initiation of 90nm mobile parts supplies, but has not released global statements on 90nm desktop products, even though was able to confirm shipments under requests. It is unclear whether the company plans to mark the release of 90nm server chips.

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“We pay close attention to AMD’s public statements, so we knew they had not announced any 90nm desktop products in the past three months. When we inquired as to why there had been no announcement, they told us the new products perform exactly like the 130nm processors they replace, and drop into the same sockets, so they didn’t think it was all that important,” a report of Insight 64 analyst firm claims.

1H 2005 – All Go 90nm?

In the first half of 2005 AMD plans to continue supplying its 90nm processors for servers released in 2004 and plans no updates in the server space. Obviously, AMD will continue to sell its 130nm AMD Opteron and AMD Athlon MP products.

At the same timeframe the company has two new desktop AMD Athlon 64 products code-named San Diego and Venice. The former is expected to be a SKU for AMD Athlon 64 FX and powerful AMD Athlon 64, the latter is mainly intended to operate as mainstream AMD Athlon 64. Besides, AMD plans to release a new incarnation of its Sempron chip code-named Palermo. According to the roadmap, AMD is expected to cease manufacturing of 130nm AMD Athlon 64 in the first half of 2005.

The latest roadmap also claims AMD to substitute the current Low Voltage AMD Athlon 64 (formerly named Oakville) with code-named Lancaster processor in 1H 2005. Current Mobile AMD Athlon 64 made using 130nm process technology will be changed for 90nm SOI part called Newark. AMD Athlon 64 processor for desktop replacement notebooks will continue to be made using 130nm SOI fabrication process, but will reach the end of life in 2H 2005. Low Voltage AMD Mobile Sempron that is made using 90nm will continue to ship throughout the first half of the year, while AMD Mobile Sempron product will face its core change to 90nm SOI product called Georgetown.

2H 2005 – Dual-Core Era Begin at AMD

As expected, in 2H 2005 AMD releases its dual-core AMD Opteron processors 100-, 200-, 800-series named Denmark, Italy and Egypt. A little bit later code-named Toledo processor will bring dual-core technology to workstations and high-end desktops.

Currently AMD has no serious plans for desktop and mobile families updates in the second half of 2005, the only new chips officially listed on the roadmap are Roma and Albany – Mobile AMD Sempron chips produced using 90nm SOI technology.

Details Unclear

AMD’s roadmaps typically give very brief understanding of the company’s plans, the documents lack any exact product details and timeframes. Still, AMD’s cautious step-by-step strategy is evident even from this type of roadmaps with the background known from external sources: AMD first transits to new fabrication process, then enables certain minor features, such as memory controller tweaks or SSE3 instructions and only then steps to major upgrades, e.g., dual-core implementation.