The prototype Cell microprocessor produced using 90nm process technology incorporates one dual-threaded PowerPC core and eight so-called synergistic processing units (SPEs) intended for floating-point calculations, the most demanding tasks in entertainment, workstation and server systems. The PowerPC core is projected to have 32KB L1 cache and 512KB L2 cache, while each of the SPEs will have 256KB of cache.
Die size of the current chip is relatively large – 221 square millimeters, so is the number of transistors – 234 million. The size of the die is approximately the same as that of Intel’s dual-core
Another advantage of Cell is to support multiple operating systems, such as conventional operating systems (including Linux), real-time operating systems for computer entertainment and consumer electronics applications as well as guest operating systems for specific applications, simultaneously, providing virtualization capabilities.
The processor code-named Cell has built-in Rambus XDR memory interface, capable of data rates of 3.20GHz to 8.0GHz. The chip also uses FlexIO processor buses, formerly codenamed Redwood that are capable of running up to 6.40GHz data rates providing bandwidth more than four times faster than best-of-class processor buses available today.
Initial production of Cell microprocessors is expected to begin at IBM’s 300mm wafer fabrication facility in
IBM, Sony Group and Toshiba expect to promote Cell-based products including a broad range of industry-wide applications, from digital televisions to home servers to supercomputers. Sony’s highly-anticipated PlayStation 3 console is projected to use Cell microprocessor.