X-bit labs

Intel Merom to Be Pin-to-Pin Compatible with Yonah – Intel Exec.

Category: CPU

by Anton Shilov

[ 10/19/2005 | 06:35 PM ]

Intel Corp. disclosed certain specifications of its code-named Merom processors, which is slated to come in the second half of 2006 and utilize fully new architecture. An important point is that Merom will be compatible with mobile platforms designed for Intel Pentium M processor based on the Yonah core.

The code-named Merom processor will feature 14-stages pipeline, down from 31 or more stages found in current Intel Pentium (Prescott) designs, 4-issue out-of-order execution engine as well as improved performance of the floating-point unit (FPU). This greatly showcases the substantial difference from the current NetBurst chips that have very deep pipeline and cannot boast with really high-performance FPUs. Furthermore, 14-stages pipeline is deeper compared to AMD Athlon 64’s 12-stages pipeline, which, on the one hand, allows slightly higher clock-speeds compared to the AMD64 architecture, but, on the other hand, may mean a bit lower efficiency.

“With our products, which are developed under the code names Conroe, Woodcrest and Merom [we will say goodbye to NetBurst],” said Patrick Gelsinger, senior cice president and general manager, digital enterprise group at Intel Corp in an interview earlier this year.

Additionally, a being dual-core processor made on a single piece of silicon, Merom will sport L1-to-L1 cache transfer as well as, possibly, unified L2 cache (up to 4MB) for better performance in applications that heavily rely on threading.

In an interview with DigiTimes web-site Intel’s Vice president of mobility group and general manager of the mobile platforms group Shmuel Eden said that the world’s largest chipmaker intends to launch Merom as pin-to-pin compatible with Yonah, which may mean that systems originally designed for Yonah may be upgraded to support the future chips by installing a new BIOS. Provided that code-named Napa platform intended for Yonah also supports Merom, the latter should operate using 667MHz Quad Pumped Bus. Besides, Merom is expected to have a bit more advanced techniques to preserve power.

“The Pentium 4 has a very deep pipeline. That was among other things necessary for the high clock-speeds, however, it caused lower efficiency in terms of high power consumption and performance. We decided for a number of reasons to employ an architecture less deep pipeline. In this regard that resembles rather the Pentium III. But some of the functions we introduced with the NetBurst, will also be found in the new architecture,” Mr. Gelsinger added referring to technologies like Hyper-Threading and Virtualization. In addition, the future chips will have to support the whole breed of desktop features, including virtualization capabilities, LaGrande technology, 64-bit capability in addition to EDB, EIST and iAMT2.