Intel Corp. said in a statement that it would ship its next-generation Intel Xeon processor MP for multi-processing servers for evaluation to customers before the end of this year. The chip is produced using 65nm technology and production of a high-end product with large amount of transistors may mean that the fabrication process in mature enough and the part will be launched on time.

The world’s largest chipmaker said that the Xeon MP processor with two executive engines code-named Tulsa will be commercially released in the second half of 2006 and will succeed the current Paxville MP design, which is made using 90nm process technology. Even though the code-named Tulsa will be made using 65nm process technology and will feature certain enhancements over the Xeon MP code-named Paxville, e.g., shared level three cache, it will still be based on the NetBurst micro-architecture. 

Tulsa will have 16MB of shared L3 cache and will be compatible with infrastructure developed for Intel Xeon 7000-series processors, which means that it should be available for 667MHz and 800MHz processor system busses. No additional information about the code-named Tulsa processor, e.g., clock-speeds, thermal design power and others, was published.

In October, Intel updated its Intel Xeon processor MP roadmap: it shelved processor code-named Whitefield and platform code-named Redland in favour of the chip called Tigerton and platform named Caneland. Tigerton will be based on the next-generation architecture from Intel, whereas Caneland will bring in a new bus for processors as well as support for Fully-Buffered Dual In-Line Memory Modules (FB-DIMMs) to multi-processor servers.