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CORRECTION: Correcting processor system bus speed for 2.93GHz processor code-named Woodcrest.

Intel Corp.’s forthcoming micro-architecture promises to be tailored for both high frequencies and increased performance per clock, which will be the reason why the flagship server microprocessor Woodcrest will come out with up to 2.93GHz clock-speed, not much lower compared to today’s dual-core server chips that are based on the NetBurst architecture.

Intel code-named Woodcrest microprocessor will feature 1066MHz processor system bus and will operate at up to 2.93GHz in the second half of 2006, according to slides presumably from Intel’s roadmap which are signed as Intel Confidential and were published at HKEPC web-site. The new chips will be marketed under the well-known Xeon name, the pictures suggest. There will be server processors with 1333MHz processor system bus from Intel Corp.

The Woodcrest processors will be made using 65nm process technology and will be compatible with LGA771 socket as well as code-named Blackford chipset. It is unknown whether the Woodcrest central processing units (CPUs) will be drop-in compatible with Bensley platform which is slated to arrive shortly.

Earlier Intel Corp. officially confirmed that the next-generation Woodcrest chips will have 1333MHz processor system bus (PSB) and core-logic to support the chip will be able to handle two of such busses. Such technology is called dual independent bus (DIB) and is also to be supported on Intel’s code-named Blackford chipset that will be able to work with two dual-core Dempsey processors using independent PSBs.

Intel’s code-named Woodcrest dual-core processors are slated to be shipped in the second half of 2006, according to Intel’s roadmap.

Given that Intel’s server processors typically utilize technologies that are also used on desktops or were previously used on desktops, it is highly likely that Intel’s forthcoming desktop chips that are to be available in 2006 will support 1333MHz Quad Pumped Bus. With higher speed busses Intel’s server processors are likely to offer much higher performance levels compared to what is available now, which will add pressure on rival Advanced Micro Devices.

Intel has confirmed that processors code-named Merom, Conroe and Woodcrest would not be powered by the NetBurst micro-architecture that powers contemporary Intel Pentium 4 and Intel Xeon chips. Besides new micro-architecture, which is expected to feature shorter pipeline and high performance per clock, the chips will also sport capabilities like virtualization capabilities, LaGrande technology, 64-bit capability in addition to EDB, EIST and iAMT2.

The code-named Merom processor will feature 14-stages pipeline, down from 31 or more stages found in current Intel Pentium (Prescott) designs, 4-issue out-of-order execution engine as well as improved performance of the floating-point unit (FPU). This greatly showcases the substantial difference from the current NetBurst chips that have very deep pipeline and cannot boast with really high-performance FPUs. Furthermore, 14-stages pipeline is deeper compared to AMD Athlon 64’s 12-stages pipeline, which, on the one hand, allows slightly higher clock-speeds compared to the AMD64 architecture, but, on the other hand, may mean a bit lower efficiency.

Discussion

Comments currently: 13
Discussion started: 02/10/06 01:54:00 PM
Latest comment: 02/15/06 10:11:00 PM
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[1-3]

1. 
One of your better written articles, with a lot of good background information to flesh out the current point.

However, additional stages do not mean lower IPC, necessarily, nor do they necessarily allow for higher clock speeds. The perfect example is the Athlon 64 which has additional stages for increased IPC, not for clock speed.

You only reach increased clock speeds when you spend more stages on the same function and remove the bottleneck. So, if I use three cycles instead of two for whatever function, that particular part can run at higher clock speeds, and presuming it was a limiting factor, the processor can.

If I add additional stages that do something that was not being done, or is now being done better, it is not going to add to clock speed. I bring this up because my suspicion is that Intel may have added a stage or more for scheduling or stages that are in some way related to feeding the extra integer pipeline. I could very easily be wrong, but when you figure that AMD doesn't know how to do this, and Intel didn't with the Pentium III and Pentium 4, it could be they need an extra stage or two to help with scheduling instructions so the extra pipeline is actually utilized sometimes. Again, just speculation, but what isn't speculation is that the extra stages in the A64 were for IPC and not extra clock speed. So, it's a bad oversimplification to make that assumption. It might be better to say that generally longer pipelines lower IPC and increase clock speeds, but not in all instances.

One last point, the Pentium III had a longer pipeline than the Athlon, but couldn't hit the same clock speeds. So, as a generality, OK, but anything more than that is disinformation.
[Posted by: TA152H  | Date: 02/10/06 01:54:00 PM]
+ expand thread (2 answers)

2. 
2,93 = 333,33 * 8,8?
[Posted by: joshua  | Date: 02/11/06 07:56:11 AM]

3. 
I'll only believe this when you can buy it. Frankly Intel hasn't hit an ontime release on anything they've laid out on any roadmap a year ahead of time, in about 3 years. Merom is highly likely to not come till 2007. Conroe in July is a pipe dream, smokin something alright.

They are good in what they do, but on time they are not. However they thrive on letting folks believe they might actually have a "better" product soon.

Dear Intel. Show us the goods. Like a working model chip? Nope!

lol


(sorry my cynical side came on strong)
[Posted by: Anemone  | Date: 02/11/06 03:21:56 PM]
+ expand thread (8 answers)

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