International Business Machines has announced at Microprocessor Forum Fall 2006 that the next-generation Power6 processor for blade servers and similar applications will run at up to 5GHz and will still contain only two processing engines. By contrast, Intel’s and AMD’s processors for similar markets expected to be available in 2007 will have four cores and will run at much lower clock-speeds.

The new Power6 central processing units will reportedly run at 4GHz – 5GHz clock-speeds, will contain 8MB of level-two cache and will have “link to external memory” with 75GB/s bandwidth, according to EETimes web-site. The chip will have the same execution pipeline as the current Power5 MP970, but will effectively double the bandwidth and clock-speed of the existing part, which operates at up to 2.50GHz. Nevertheless, the chip will still consume the same amount of power.

“We needed to scale the whole system. When you just pack on more cores and don’t scale the cache and memory bandwidth you can’t really scale CPU performance as well,” said Brad McCredie, a fellow in IBM’s systems and technology group.

The processor will be made using 65nm IBM’s silicon-on-insulator (SOI) and strained silicon process technology. The web-site also claims that IBM applied new techniques in variable gate lengths and variable threshold voltages to squeeze maximum performance per Watt at the transistor level. The chip can be fully operated at as little as 0.8V.

IBM’s latest central processing units (CPU) feature power saving technology called PowerTune. The frequency and voltage of both cores can be scaled downward to reduce the power during periods of reduced workload. For further power savings, each core can be independently placed in a power-saving state called “doze”, while the other core continues operation. Moreover, one of the cores can be completely de-powered during periods of less stringent performance requirements.

The introduction of Power6 lets IBM to refresh for its existing p-series server line in mid-2007.