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Intel Corp. has demonstrated its new multi-processor server platform along with its next-generation server chip for multi-processor machines. The demonstration is poised to tell the company’s clients and investors that the new Intel Xeon MP product is essentially ready and the company is on-track to ship it in the Q3 of 2007. 

Intel Demos Tigerton 

Intel was tight-lipped in regards the code-named Tigerton processor details, according to media reports, however, it was still announced that the new chip along with the Caneland platform will use a chipset code-named Clarksboro which supports fully-buffered dual-in-line memory modules (FB-DIMMs) and will have four dedicated processor buses (one link per processor), which means that Tigerton processors will not have built-in memory controller and the whole platform will still use several processor system buses instead of one common interconnection akin to the HyperTransport bus. 

Intel’s Xeon MP “Tigerton” processor is the company’s first chip for MP machines that is based on the energy efficient Core 2 micro-architecture. The chip was included into the roadmap back in late 2005 to substitute the code-named Whitefield microprocessor just months after the company publicly demonstrated a roadmap at Intel Developer Forum Fall 2005 that showcased Whitefield and Dunnington chips due to arrive in 2007. Intel said that changes in plans were conditioned by an intention to offer higher performance. 

Platform Details Unclear 

The fundamental difference between the Caneland platform and the Redland platform is that the former supports so-called dedicated high-speed interconnect. The bottom line, according to what Intel claims, is that Whitefield chips were supposed to share a processor system bus in multiprocessor system, whereas Tigerton processors are expected to get dedicated interconnection to the rest of the system. 

Earlier it was anticipated that in “the middle of the decade”, or the year 2007, as some implied, the world’s largest chipmaker unifies its Intel Xeon and Intel Itanium platform so that Xeon system builders could adopt Itanium chips without switching to different hardware. In Summer 2005 an Intel partner said that in 2007 Intel server platforms would use common serial interconnect (CSI) bus instead of traditional processor system bus and some processors will have built-in memory controller. The first of such chips was projected to be Tukwila, a multi-core Intel Itanium processor, which is, after the Montecito delay, scheduled for 2008.  

It is highly likely that the “dedicated high-speed interconnect” of the Caneland has is a more advanced version of the [dual] independent bus used in the Truland platforms and Bensley platforms. 

Even though four dedicated processor links of the Clarksboro/Caneland may not be as efficient as the HyperTransport, it will still be much faster than Intel’s multi-processor server infrastructure today. The current MP platform from Intel puts two dual-core microprocessors on the same 800MHz/64-bit bus, meaning that every chip has 3.20GB/s of bandwidth, much less than current desktop microprocessors. In order to compensate relatively low processor system bus bandwidth, Intel has to integrate large 16MB level three cache (L3) into its current Intel Xeon 7100-series microprocessors. Intel did not specify the capacity of L3 cache of the Tigerton microprocessors. 

Even though Intel has not acknowledged that Caneland does not support Itanium 2 processors, it is highly likely that it does not, as the world’s largest chipmaker would hardly miss an opportunity to demonstrate compatibility – on the platform level – between various series of its microprocessors.


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