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Despite of the fact that Intel Corp.’s desktop and mobile processors produced using 45nm process technology are set to emerge only in the first quarter of next year, the firm plans to make available its quad-core processors for dual-socket servers already this year.
Intel’s code-named Harpertown processor, which is rumoured to be a derivative of Intel’s code-named Yorkfield chips, is set to be available for Intel’s customers in Q4 2007, a quarter earlier than its desktop and mobile counterparts, according to documents seen by X-bit labs. The new chip will be made using 45nm process technology and will sport a number of new features, which are projected to boost its performance. It is known that quad-core Intel Xeon “Harpertown” processors will be aimed at dual-processor (DP) servers and workstations, though, exact specifications of the new central processing unit (CPU) remain unclear.
The new quad-core Intel Xeon “Harpertown” processors will fit into Intel 5000P chipset-based infrastructure aimed at performance and volume DP servers. For value DP servers Intel is set to introduce Intel 5100 chipset that sports 1066MHz and 1333MHz processor system busses (PSBs) along with
Intel Xeon-based workstation platforms will also get updates: for DP machines Intel recommends using code-named Seaburg chipset that supports 1066MHz and 1333MHz PSBs as well as FB-DIMM memory, whereas for uni-processor (UP) machines the company advices to use Intel X38 core-logic, which is also aimed at enthusiasts.
Intel announced in March that the new-generation chips produced using 45nm process technology and featuring Core 2 micro-architecture, will have greater instructions per clock (IPC) execution, which means that they will be faster and more efficient even at the same clock-speeds with the current generation chips. Besides, the new chips will be able to run at higher clock-speeds compared to today’s Core 2 Duo and Core 2 Quad products.
The major micro-architectural improvements for new Intel Core 2 processors, besides SSE4 instruction set, include the so-called Unique Super Shuffle Engine and Radix 16 technique. The Super Shuffle Engine is a full-width, single-pass shuffle unit that is 128-bits wide, which can perform full-width shuffles in a single cycle. This significantly improves performance for SSE2, SSE3 and SSE4 instructions that have shuffle-like operations such as pack, unpack and wider packed shifts. This feature will increase performance for content creation, imaging, video and high-performance computing. Radix 16 technique, according to Intel, roughly doubles the divider speed over previous generations for computations used in nearly all applications. In addition, Intel also improved virtualization technology as well as added some features to dynamic acceleration technology, which is supposed to boost single-threaded applications’ performance on multi-core chips.
Intel did not comment on the news-story.
