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Advanced Micro Devices will not enable new-generation HyperTransport technology for its dual-processor (DP) and multi-processor (MP) server platforms for quite a while in order to allow customers to install next-generation 45nm server chips into infrastructure introduced back in 2006.

AMD Opteron quad-core and dual-core processors code-named Shanghai, which are expected to be released in the second half of 2008, will use AMD’s K10 micro-architecture that will be present already in the code-named Barcelona processors, but will contain some performance enhancements. Thin 45nm process technology will allow AMD to install 512KB of L2 cache per core as well as 6MB of unified L3 cache, which is a significant enhancement compared to Barcelona.

But despite of some improvements, AMD’s code-named Shanghai solutions will retain compatibility with dual-channel registered-DDR2 memory as well as LGA1207 form-factor and HyperTransport 1.0 bus, which will allow server makers and their customers to easily upgrade current platforms to the new microprocessors.

Historically AMD used one platform for two generations of its processors, e.g., the original 940-pin platform for single-core AMD Opteron chips could also support dual-core processors. The 1207-pin infrastructure originally introduced for dual-core DDR2-supporting AMD Opteron chips also promised support for quad-core processors, but, apparently, it will also support enhanced quad-core chips as well.

It is unclear when AMD introduces a platform to support its octa-core central processing units, however, it is highly likely that a platform for 8-core processors will use DDR3 memory.

Officials from Advanced Micro Devices did not comment on the news-story.

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