Intel Corp. plans to start shipping its quad-core microprocessors made using next-generation 45nm process technology for revenue in the fourth quarter of the year, sources familiar with the company’s plans revealed. But the world’s largest producer of x86 microprocessors is unlikely to release those chips for end-users this year.

Even though Intel’s code-named Yorkfield processors with four processing engines are still due to be introduced in Q1 2008, Intel Corp. will begin to ship them in Q4 2007 in order to allow computer makers to stockpile a significant amount of such chips before their official launch. Intel’s dual-core code-named Wolfdale chips will still begin to ship in Q1 2008, according to sources.

Such roll-out pattern for Intel is very common: it began to ship Dothan, Yonah, Cedar Mill/Presler as well as some other chips in the recent years about a quarter ahead of formal introduction. Moreover, even though 65nm-based code-named Presler processors (Pentium D 900-series) were launched in Q1 2006, Intel still released a number of such chips late in 2005 and allowed the press to review them.

Quad-core code-named Yorkfield processors are projected to feature up to 12MB of L2 cache, 1333MHz processor system bus and clock-speeds in the range of 3.33GHz.

Intel announced in March that the new-generation chips produced using 45nm process technology and featuring Core 2 micro-architecture will have greater instructions per clock (IPC) execution, which means that they will be faster and more efficient even at the same clock-speeds with the current generation chips. Besides, the new chips will be able to run at higher clock-speeds compared to today’s Core 2 Duo and Core 2 Quad products.

The major micro-architectural improvements for new Intel Core 2 processors, besides SSE4 instruction set, include the so-called Unique Super Shuffle Engine and Radix 16 technique. The Super Shuffle Engine is a full-width, single-pass shuffle unit that is 128-bits wide, which can perform full-width shuffles in a single cycle. This significantly improves performance for SSE2, SSE3 and SSE4 instructions that have shuffle-like operations such as pack, unpack and wider packed shifts. This feature will increase performance for content creation, imaging, video and high-performance computing. Radix 16 technique, according to Intel, roughly doubles the divider speed over previous generations for computations used in nearly all applications. In addition, Intel also improved virtualization technology as well as added some features to dynamic acceleration technology, which is supposed to boost single-threaded applications’ performance on multi-core chips.