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Advanced Micro Devices has announced a technology, which will allow future multi-core microprocessors to choose the best way of execution themselves, improving performance and making it easier to create software for multi-core microprocessors. The new tech may also eventually help the world’s second largest chipmaker to promote general purpose computing on graphics processors.

For years programming for multi-processor or multi-core machines has been a complex task, as software developers had to parallelize their code to take advantage of numerous processing engines. In the recent years this task has gained importance dramatically, as dual-core chips became widespread, however, efficient programming for such computers did not become much easier than before. But Advanced Micro Devices believes that it had found a way to solve this, as its newly-introduced Light-Weight Profiling (LWP) technology will allow chips to decide the most efficient way of execution themselves.

According to AMD, LWP is designed to enable code to make dynamic and real-time decisions about how best to improve the performance of concurrently running tasks, using techniques such as memory organization and code layout, with very little overhead. The LWP is a set of hardware features in future versions of microprocessors by AMD, thus, it is very likely that a part of the technology is a new set of instructions found in the forthcoming micro-architectures from AMD, such as Bulldozer.

“AMD understands the challenges developers face when creating multi-threaded software, and so we are taking a step to evolve new methods to ensure that software applications are optimized for multi-core technology,” said Earl Stahl, vice president, software engineering at AMD. “In the spirit of AMD’s commitment to open innovation and fostering industry discussion, we are making the Light-Weight Profiling specification available to encourage discussions with the developer community around how to make native and managed code perform better in multi-core computing environments.”

In fact, hardware parallelization is not something particularly new. Back in late 2005 NEC introduced a complier that was meant to be loaded onto a field programmable logic array (FPGA) and automatically parallelize software. The different between NEC’s technology and AMD’s proposal is that the latter promises real-time optimizations, whereas NEC’s technology was aimed at faster offline optimizations of programs.

Potentially, real-time increases in efficiency of execution may lead to a hardware arbiter, which will be able to decide on which computing engine to use. Given that AMD plans to introduce Fusion microprocessors that will feature both general-purpose (GP) central processing unit (CPU) and graphics processing unit (GPU), the LWP technology may eventually be able to handle certain tasks to GPU, which is a highly-parallel computing engine itself. On the other hand, LWP ensures that software performance scales according to the amount of symmetric computing engines.

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