Advanced Micro Devices on Thursday announced availability of Streaming SIMD (Single Instruction, Multiple Data) Extensions (SSE5) specification. The new instructions promise higher performance and execution efficiency and will be implemented into microprocessors due in 2009.
The 170 new SSE5 instructions will improve central processing units’ (CPUs’) performance in high performance computing (HPC), multimedia and security-related applications, according to AMD. The new set includes such instructions as fused multiply accumulate (FMACxx), integer multiply accumulate (IMAC, IMADC), permutation and conditional move, vector compare and test, precision control, rounding, and conversion instructions.
AMD explained that by increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective 3-operand instruction. The ability to execute 3-operand instructions is currently only possible on certain RISC architectures.
Fused Multiply Accumulate the 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The FMAC instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector math1ematics and other performance-intense applications.
The first microprocessors from AMD that support SSE5 will be those code-named Bulldozer expected to become available in 2009.
“Chip advancements and software improvements go hand-in-hand, to the benefit of consumers and enterprises alike. The impact of our designs are best realized when AMD-based servers, PCs and devices enable software to more effectively solve every-day problems and enhance every-day experiences,” said Phil Hester, senior vice president and chief technology officer, AMD.
By making the SSE5 specification available to developers today, AMD expects to ease the adoption of the new instructions for tool providers and software vendors who develop these performance-intense applications.
“By announcing our plans to add SSE5 instructions to the x86 instruction set ─ and by making the specification available today ─ we are enabling open and collaborative software innovation that will bring AMD’s advancements to life for our customers and end-users,” Mr. Hester added.