X-bit labs

Via Technologies Unveils New Breed of Central Processing Units.

Category: CPU

by Anton Shilov

[ 01/29/2008 | 10:18 PM ]

Via Technologies, a struggling designer of chipsets, graphics chips and microprocessors, announced recently its new family of microprocessors that offer high clock-speeds, 64-bit capability, out-of-order execution along with promised tangible performance improvements. It remains to be seen whether single-core microprocessors will be able to compete against modern chips from AMD and Intel.

“Today is an exciting day for everyone at Centaur. With a team of less than one hundred first-class engineers, we have created from scratch the world’s most power-efficient x86 processor architecture with state of the art features, outstanding performance, and flexible scalability for the future,” said Glenn Henry, president of Centaur Technology, a wholly owned subsidiary of Via Technologies that develops microprocessors.

Via Isaiah is the first x86 processor from Via Technologies that features 64-bit instruction set along with a superscalar and out of order execution engine, macro-fusion and micro-fusion functionality, advanced branch prediction mechanism, advanced floating point unit as well as support for virtualization technology and Via PadLock security engine.

Since Via Technologies has been concentrating primarily on low-power central processing units (CPUs) recently, the new chips that belong to the Isaiah family will also feature Adaptive PowerSaver Technology that further reduces power consumption and improve thermal management, including the unique TwinTurbo dual-PLL implementation, which permits smooth transitions between activity states within one clock cycle, ensuring always-on service and minimize latency, as well as new mechanisms for managing the die temperature.

The first Isaiah processors will support clock-speed up to 2.0GHz, will use 800MHz – 1333MHz processor system bus (PSB) and will be pin-to-pin compatible with Via C7 chips. The CPUs will have two 64KB L1 caches and 1MB exclusive L2 cache with 16-way associativity.

Processors implementing the Via Isaiah micro-achitecture are expected to start shipping in the first half of 2008 and will be manufactured using an advanced, low power 65nm process.