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At CeBit show that is currently on in Hanover, Germany, AMD for the first time demonstrated their quad-core processors with K10 micro-architecture manufactured with 45nm process. The processors were produced in Dresden, Germany, in AMD’s Fab 36 300mm manufacturing facility, using an advanced 45nm process co-developed with IBM. The first 45nm chips demonstrated by AMD include the “Shanghai” product for server and “Deneb” for desktop platforms.

This fact proves that AMD is on track to meet key production milestones, which support OEM and channel product delivery plans. AMD is ramping production of its first 45nm products in the first half of 2008 and expects 45nm products to be available in the second half of 2008.

Key innovations within AMD’s 45nm process are scheduled to include Immersion Lithography, Fourth-generation Strained Silicon, Ultra-low-k Dielectrics, and High-k/metal Gates. However, the initial 45 nm CPU generation will not use high-k dielectric metal gate technology. AMD believes that it can be “competitive” without high-k at this time, but high-k is an option to be introduced at a later stage of 45 nm production.

These enhancements are aimed primarily at improving AMD’s transistor designs and interconnect circuitry to enable sustained linear increases in processor and platform performance-per-watt, while also overcoming inherent challenges introduced from continued reduction of transistor size.

45nm Deneb and Shanghai processors are expected to have their shared L3 cache increased to 6MB. As a result of transition from 65nm to 45nm production technology, they should be able to drop processor TDP one step down. The top CPUs should have their maximum TDP reduced from 140W to 125W. More mainstream quad-core processor models should have their TDP dropped from 125W to 95W with the transition to 45nm process. They also expect the clock speed of the top CPU models to increase at least to 2.8-3.0GHz. All 45nm desktop AMD processors scheduled to be released this year will be designed for Socket AM2+ and will support DDR2-1066 SDRAM. Only in Q1 2009 we should see Socket AM3 processors that will also support DDR3-1333 in addition to their compatibility with DDR2 memory.

Discussion

Comments currently: 31
Discussion started: 03/04/08 12:40:52 PM
Latest comment: 05/31/08 09:57:00 AM
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1. 
Second half 2008 = December, presumably ...
0 0 [Posted by:  | Date: 03/04/08 01:26:10 PM]
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2. 
Well I guess they had to skip over 55nm. This is doubly good for AMD since they are likely to use 45nm in their GPUs as well. I think they will try out hi-k on their mainstream GPUs first before using that technology on their CPUs. Right now though I just want to see their quad core CPU's without the TLB bug.
0 0 [Posted by:  | Date: 03/04/08 01:47:57 PM]
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3. 
Did they actually demo a System with a 45nm CPU or just show a wafer? That seems like a very big difference to me.
Regardless, good luck AMD with your shrinking. They don’t need much luck as they are experts at shrinking things; e,g.share price, profits, credibility.
0 0 [Posted by:  | Date: 03/04/08 03:34:57 PM]
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4. 
What demo? All I find is an announcement. AMD, show us the real beef please...

Even with TLB fixed, ain't gonna be faster than current Intel's Core 2 Quads. Anyway, by the time their K10 is really ready, watch out for Nehalem. If the leaked Sun slides are anything to go by, and if true then Nehalem is truly a monster.

I guess Intel will be waiting to spring another coup again, or maybe not if 45nm K10 turns out to be a dud like Barcey...
0 0 [Posted by:  | Date: 03/04/08 04:11:01 PM]
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- collapse thread

 
Ace Hardware has some good estimates of FP/INT performance of Shanghai versus Nahalem. AMD can't see to catch a break these days. They finally get on track only to face a "tock" improvement from Intel.
0 0 [Posted by:  | Date: 03/04/08 08:14:28 PM]
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im going hold judgement on that, but sinds they are reintroducing Hyper-threading im going to take these numbers with a pinch of salt and wait for some realworld benchmarks.
hyper-treading had a way giving great results in synthetic benchmarks but then falling flat on its face in real world apps (often you where better off turning it off).

now ofcourse software is more threaded then in the p4 time but nehalem is also not a long-pipelined cpu anymore which was the reason for HT in the first place.
0 0 [Posted by:  | Date: 03/05/08 01:18:30 AM]
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They may be calling it HT again, but really the purpose will be somewhat different--much more akin to traditional SMT rather than the hack needed in the P4 due to the inaccessibility of deeply pipelined execution units. Processors nowadays have much more cache and much better memory latency figures than P4s did, so this iteration of HT should be a lot more effective at reducing thread switch latency and all the penalties that go along with that outside the execution pipeline itself.
0 0 [Posted by:  | Date: 03/05/08 05:45:45 AM]
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the more cache en lower latency ect only mean CPU's have less reason to use HT because they can keep their pipeline full without it.
0 0 [Posted by:  | Date: 03/06/08 03:30:53 AM]
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