Isaiah will be going againts Intels Atom/Celeron/Core Duo/Low Voltage Core2 and AMD Puma. Early reviews published shows that early samples of Isaiah is as power as Intel Core processors....so a dual core verison will be on par/surpass Core Duo/Atom depending on frequency.
Via Technologies, a struggling designer of core-logic sets and x86 central processing units, will reportedly utilize new process technology and introduce processors with two cores by the end of next year. While this will boost competitive position of Via’s chips, the company will still be unable to offer alternative for processors by Advanced Micro Devices or Intel Corp. on the mainstream marker.
By the end of 2009 Via Technologies will adopt 45nm process technology and launch its first dual-core microprocessors, a news-story at DigiTimes web-site claims. The dual-core central processing units from Via will be based on Isaiah micro-architecture and are likely to be made by Fujitsu in Japan.
Via reportedly unveiled more details of its first CPUs based on Isaiah micro-architecture. The chips will feature a clock-speed of 2.0GHz, a V4 Bus speed from 800-1333MHz, and two 64KB L1 cache and 1MB L2 cache with 16-way associatively. The processors, which are made using 65nm process technology at Fujitsu, are pin-to-pin compatible with the Via C7 processors.
Via Isaiah is the first x86 processor from Via Technologies that features 64-bit instruction set along with a superscalar and out of order execution engine, macro-fusion and micro-fusion functionality, advanced branch prediction mechanism, advanced floating point unit as well as support for virtualization technology and Via PadLock security engine. Eventually there will be dual-core Isaiah CPUs, though, no details are available at this time.
The new chips that belong to the Isaiah family will also feature Adaptive PowerSaver Technology that further reduces power consumption and improve thermal management, including the unique TwinTurbo dual-PLL implementation, which permits smooth transitions between activity states within one clock cycle, ensuring always-on service and minimize latency, as well as new mechanisms for managing the die temperature.