Nvidia Corp., the world’s largest supplier of standalone graphics processing units (GPUs), plan to actively promote Via Isaiah microprocessors together with Via Technologies and even take part in the formal launch. Initially, Nvidia only plans to support Isaiah with its discrete graphics chips, but later on the company intends to deliver a core-logic set for Via’s processors too.

“We are participating in the launch. We wish to work with them in demonstrating any number of different visual computing applications,” said Drew Henry, general manager of Nvidia’s platform products division, in an interview with Cnet web-site.

At first, Via Isaiah processors will be release with support of Via’s own core-logic and with an Nvidia GeForce graphics processor, but sometime next year Nvidia and Via Technologies plan to launch so-called VN platform that includes a chipset by Nvidia with GeForce graphics core integrated as well as Via Isaiah microprocessor.

Nvidia, which competes heavily against ATI, graphics product group of Advanced Micro Devices, and Intel Corp. is facing pressure on the market of chipsets for microprocessors from AMD as well as Intel and hopes to popularize VN platform in order to stay in the chipset business. Meanwhile, Via Technologies does need a strong partner, such as Nvidia, to promote its microprocessor products.

Via Isaiah is the first x86 processor from Via Technologies that features 64-bit instruction set along with a superscalar and out of order execution engine, macro-fusion and micro-fusion functionality, advanced branch prediction mechanism, advanced floating point unit as well as support for virtualization technology and Via PadLock security engine. Eventually there will be dual-core Isaiah CPUs, though, no details are available at this time.

The new chips that belong to the Isaiah family will also feature Adaptive PowerSaver Technology that further reduces power consumption and improve thermal management, including the unique TwinTurbo dual-PLL implementation, which permits smooth transitions between activity states within one clock cycle, ensuring always-on service and minimize latency, as well as new mechanisms for managing the die temperature.