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Intel Corp., the world’s largest maker of microprocessors, has announced its new breed of processors aimed at dual-processor servers and workstations. The new Xeon chips powered by Nehalem micro-architecture feature integrated memory controller, high-speed Quick Path Interconnect point-to-point bus and sport other technology advantages. Intel considers new Xeon processor as its most important chip since Pentium Pro.

“The Intel Xeon processor 5500 series is the foundation for the next decade of innovation. These chips showcase groundbreaking advances in performance, virtualization and workload management, which will create opportunities to solve the world's most complex challenges and push the limits of science and technology,” said Patrick Gelsinger, senior vice president and general manager of Intel's digital enterprise group.

The new enterprise-class chips can automatically adjust to specified energy usage levels, and speed data center transactions and customer database queries. The Intel Xeon processor 5500 series, previously codenamed "Nehalem-EP," offers several breakthrough technologies that radically improve system speed and versatility. Technologies such as Intel Turbo Boost Technology, Intel Hyper-Threading Technology, integrated power gates, and Next-Generation Intel Virtualization Technology (VT) improved through extended page tables, allow the system to adapt to a broad range of workloads.

The main architectural enhancements for Intel Xeon 5500 are triple-channel DDR3 memory controller and the Quick Path Interconnect (QPI) bus, which improves scalability of multi-processor systems. The new Xeon also support multi-threading technology similar with Intel Hyper-Threading that was first unveiled back in 2002 as well as SSE4.2 instructions.

“Nehalem is a game changer in just about every way, especially performance. It overcomes most, if not all, the potential performance roadblocks associated with multi-core configurations. It creates a foundation for future processors, and it resets performance expectations, especially for applications requiring high I/O or memory bandwidth,” said Jim McGregor, industry analyst from InStat.

Another key enhancement of Intel Nehalem is completely redesigned cache sub-system. The new chips will feature 2nd level 512 entry translation look-aside buffer (in addition to 1st level TLB) in order to further reduce the so-called TLB miss rate, a completely new feature on x86 microprocessors. In addition, Intel Xeon 5500 processors (at least, in certain implementations) will have three-level cache hierarchy: 64KB L1 (32KB for data, 32KB for instructions), 256KB L2 cache per core, 8MB L3 cache per processor.

Besides, the new processors can execute 33% more concurrent micro-ops at the same time. Additional improvements include faster unaligned cache accesses and faster synchronization primitives. In order to exclude situations when execution units stand idle, Intel also implemented new 2nd level branch predictor.

The family of Intel Xeon processors on Nehalem micro-architecture is pretty broad – 15 different models – and aimed at different markets. Pricing of the new chips varies from $188 to $1600, depending on aim, performance, power consumption and other qualities of the chip. All the chips in the initial lineup contain four processing engines, except one, which is a dual-core offering. Besides, the majority have simultaneous multi-threading technology enabled.

More than 230 unique systems based on the Intel Xeon processor 5500 series are expected to be announced by more than 70 system manufacturers around the world – including a new Intel customer, Cisco, along with Dell, Fujitsu, HP, IBM, Sun Microsystems and others.

Tags: Intel

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