ARM, a leading designer of low-power processing cores, has announced that its new ARM Cortex-A9 MPCore intellectual property is designed in accordance with TSMC’s 40nm process technology design rules. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2.0GHz, which is likely to allow the company-designed processors to compete against x86 products by Advanced Micro Devices and Intel Corp.
“The Cortex-A9 MPCore processor has already been widely accepted as the processor of choice for high-performance embedded applications across a broad spectrum of demanding consumer and enterprise devices. ARM’s parallel development of advanced, optimized physical IP components demonstrates a new level of collaborative differentiation while enabling our partners to expand their penetration into high margin domains traditionally occupied by proprietary architectures,” said Eric Schorn, vice president of marketing at processor division of ARM.
There will be two Cortex-A9 MPCore implementations for TSMC’s 40nm process:
- The Cortex-A9 speed-optimized hard macro implementation will provide system designers with an ARM processor incorporating aggressive low-power techniques. This hard macro implementation operates in excess of 2GHz when selected from typical silicon and represents an ideal solution for high-margin performance-oriented applications, according to the developer. Modern ARM chips operate at clock-speeds lower than 1GHz, hence, two times boost will indisputably offer very high performance gain.
- The Cortex-A9 power-optimized 40nm hard macro implementation delivers its peak performance of 4000DMIPS while consuming less than 250mW per CPU when selected from typical silicon.
The hard macro implementations include ARM AMBA-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area.
Each Cortex-A9 hard macro implementation also includes the CoreSight Program Trace Macrocell (PTM) which provides full visibility into the processor’s instruction flow, enabling the software community to develop code for optimal performance.
Both ARM dual-core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of L2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.
The Cortex-A9 hard macros and the corresponding optimized physical IP used to develop the speed-optimized and power-optimized implementations are available for license today with delivery in the fourth quarter of 2009. ARM’s 40nm “G” physical IP platform is also available today.