Advanced Micro Devices will initiate production of its first-processor based on Bulldozer micro-architecture in the first half of 2011, a source familiar with the plans of the world’s second largest supplier of microprocessors has revealed. Potentially, this may mean that the long-awaited micro-architecture from AMD will be available earlier than expected.
According to a source familiar with AMD’s server plans, the chipmaker plans to commence mass production of certain versions of its code-named Interlagos microprocessors with 12 or 16 cores already in the first half of 2011. Other versions of the chips, e.g. with reduced power consumption or increased performance, will still be produced in the second half of the year.
While generally AMD formally unveils microprocessors when it begins mass production or revenue shipments of its chips. However, it is not set on stone that initiation of mass production means formal announcement. From the current point of view the information means that AMD has equal chances of launching its sixteen-core or twelve-core AMD Opteron “Interlagos” processors either in the first half of the year or in the second half of the year.
AMD Opteron 6000 “Interlagos” will be compatible with AMD’s Maranello server platform with G34 (1944-pin) sockets. It is expected that Interlagos features two code-named 32nm SOI Valencia chips with six or eight cores on the same piece of substrate.
Based on the information provided by AMD during its annual Analyst Day in November, the first Bulldozer chip code-named Zambezi (which belongs to Orochi family of desktop chips, according to the firm) will feature eight x86 processing engines with multithreading technology, two 128-bit FMAC floating point units, shared L2 cache, shared L3 cache as well as integrated memory controller. AMD also states that the new CPU will feature “extensive new power management innovations”. Based on the diagram that AMD demonstrated, the company intends to dramatically improve multithreading performance of its CPUs: two INT schedulers, an FP scheduler and separate data caches for each of four cores should do the job very well.
AMD did not comment on the news-story.