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At the International Solid-State Circuits Conference (ISSCC) Advanced Micro Devices has disclosed peculiarities regarding its x86 microprocessors produced using 32nm silicon-on-insulator process technology with high-K metal gate (HKMG) technology. Apparently, AMD’s first Fusion chip code-named Llano will be able to dynamically scale clock-speeds of its x86 cores in order to boost performance or trim power consumption.

As reported, AMD Llano accelerated processing unit (APU) will have four x86 cores based on the current micro-architecture each of which will have 9.69mm² die size (without L2 cache), a little more than 35 million transistors (without L2 cache), 2.5W – 25W power consumption, 0.8V – 1.3V voltage and target clock-speeds at over 3.0GHz clock-speed. The clock-speeds will dynamically scale their clock-speeds and voltages within the designated thermal design power in order to boost performance when a program does not require all four processing engines or trim power consumption when there is no demand for resources.

In order to further reduce power consumption and enable all the aforementioned characteristics, AMD had to implement a number of innovations into the chip on process technology and design levels:

  • Core power gating: thanks to the new “power gating-to-ground” approach enabled by SOI manufacturing process, AMD can completely disconnect cores from the power grid. According to AMD, usage of NFET power gating transistor reduces power leakage versus previous power gating solutions by 10 times. Besides, ground-gating can also use the much more conductive chip package for gate supply redistribution rather than a special thick metal layer on the die.
  • Digital APM module: each of AMD’s x86 cores feature their own digital power meters which allow to measure actual load of each core very precisely and deliver accurate information to the chip’s power manager that accurately tunes each core’s clock-speed, voltage and other characteristics in accordance with the actual load. As a result, AMD’s Llano processors will be able to overclock select cores within the CPU and disconnect the others to deliver higher performance without increasing power consumption.
  • Power aware clock grid design: the new power grid design reduces clock switching power by two times, clock grid metal capacitance by 80% and the number of final clock buffers by 50%.

Interestingly, AMD has not disclosed any details regarding operation of built-in ATI Radeon HD 5000-class graphics core as well as memory controller.

AMD’s and Globalfoundries’ 32nm SOI process will use high-k metal gates, 11 copper metal layers with low-k dielectric, silicon germanium-based strained silicon to improve performance as well as second generation immersion lithography.

Tags: AMD, Llano, 32nm, Fusion, Semiconductor

Discussion

Comments currently: 1
Discussion started: 02/11/10 10:10:45 AM
Latest comment: 02/11/10 10:10:45 AM

[1-1]

1. 
1MB L2 = 8Mb x 6T cache cell ~= 50M
35M core + 50M cache = 85M
85M x 4 cores = 340M transistors

Add a 80SP GPU to that and the transistor count should exceed 500 million. That's not even figuring if there is a L3 cache. Big chip? Probably.
0 0 [Posted by: cheeseman  | Date: 02/11/10 10:10:45 AM]
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