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Intel Corp. said on Wednesday that it would begin shipments of its experimental 48-core microprocessors dubbed single-chip cloud computer (SSC) late in the second quarter of the year. The systems-based on the central processing units (CPUs) will be sent to academic institutions.

“Limited quantities of the processor will be sent primarily to academic institutions,” said Sean Koehl, technology evangelist with Intel Labs, during an event in New York on Wednesday, reports IDG News Service.

According to Intel, the 48-core chip operates at the clock-speed comparable to Intel Atom microprocessors, which means that the frequency of the microprocessors is in the range between 1.60GHz and 1.83GHz.

The prototype chip contains 24 tiles with two IA cores per each, which results in 48 cores – the largest number ever placed on a single piece of silicon. Each core can run a separate OS and software stack and act like an individual compute node that communicates with other compute nodes over a packet-based network. Every core sports its own L2 cache and each tile sports a special router logic that allows tiles to communicate with each other. A 24-router mesh network with 256GB/s bisection bandwidth. The processor sports four integrated DDR3 memory controllers, or one controller per twelve cores.

The SCC can run all 48 cores at one time over a range of 25W to 125W and selectively vary the voltage and frequency of the mesh network as well as sets of cores. Each tile (2 cores) can have its own frequency, and groupings of four tiles (8 cores) can each run at their own voltage.

One of the distinct features of the new 48-core experimental chip will be its extreme programmability. Software applications will be able to automatically control the number of cores to use at any given time and operating systems will be able to assign certain cores for auxiliary tasks. Moreover, software will be able to manage power consumption, clock-speed of individual cores or even shut them down when not needed.

The experimental 48-core CPU will help Intel and software developers to study management and scheduling mechanisms of explicitly multi-core microprocessors in order to get prepared to bring them onto the mass market. Next year, Intel plans to provide software developers more than a hundred of experimental chips for development of new software apps.

Though each core has 2 levels of cache, there is no hardware cache coherence support among cores in order to simplify the design, reduce power consumption and to encourage the exploration of datacenter distributed memory software models, on-chip. Intel researchers have successfully demonstrated message-passing as well as software-based coherent shared memory on the SCC.

The chip does seem to be extremely interesting. According to Intel, the cores are fully-fledged x86 cores and while it is unknown whether they support any extensions, such as SSE, it is understandable that they, unlike stream processors inside graphics processing engines, can perform complex operations and even run operating systems (hence, we can make a conclusion that chip level virtualization is in place).

Theoretically, the 48-core chip could even process graphics using ray-tracing method or even using traditional fixed-function pipeline if it was equipped with appropriate units. However, even if it has been equipped with GPU-specific blocks, it would have performed slower than conventional graphics processing units with up to 1600 stream processors.

One thing regarding SCC is clear: the future processors will feature tremendous amounts of cores and the general architecture of chips will be different compared to the existing microprocessors.

Tags: Intel, SCC

Discussion

Comments currently: 5
Discussion started: 04/10/10 02:03:20 AM
Latest comment: 04/13/10 08:47:15 AM
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1. 
which means that the frequency of the microprocessors is in the range between 1.60GHz and 1.83GHz.


Talk about having absolutely no work done on researching about the SCC by Xbitlabs!

The SCC can only clock at such speeds(1.60GHz/1.83GHz) on parts of the chip, specifically the mesh connecting the cores together! The cores clock at 1/2 the mesh frequency as per their presentation.

Xbitlabs used to be accurate in their articles but it seems the quality is degrading.
0 0 [Posted by: DavidC1  | Date: 04/10/10 02:03:20 AM]
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The story was written based on claims made by Intel

Mech interconnection of the SCC is clocked at ~2GHz. Mech interconnect bandwidth is between 1.5Tb/s and 2Tb/s. That is based on an Intel presentation.
0 0 [Posted by:  | Date: 04/10/10 04:07:52 AM]
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Yes, Mesh frequency is 2GHz, which connects the cores, but the cores clock at HALF the frequency of the Mesh. The article very much implies the frequency of the cores are at 2GHz(or somewhere near).Do I tell you I have a 6.4GHz chip since the QPI frequency of my i5 661 runs at 6.4GHz?
0 0 [Posted by: DavidC1  | Date: 04/11/10 02:22:44 PM]
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2. 
Well it's good that they're feeding them to the academics ... They're really stuck in the 1950's with their programming skills and most of them have absolutely no idea about SIMD let alone about threading ...
0 0 [Posted by: East17  | Date: 04/10/10 10:41:00 PM]
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3. 
and also it's not the "the largest number ever placed on a single piece of silicon" Intel already demo'd an 80core 2yrs ago at one of the tech shows
0 0 [Posted by: Athlonite  | Date: 04/13/10 08:47:15 AM]
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