Intel Corp. recently demonstrated a system based on the experimental 48-core supercomputer on chip (SCC) processor. The system appears to look like just an ordinary personal computer and seems to operate flawlessly. Unfortunately, Intel share no benchmark numbers for the prototype processor that belongs to the company’s Terascale Research program.
The experimental mainboard for the 48-core SCC is called Copper Ridge and besides the processor itself it carries a specially-designed core-logic, eight DIMM slots, necessary I/O to enable operation of the system (graphics core, graphics memory on SO-DIMM, various standard connectors as well as numerous special-purpose connectors) and other necessary components. There are no Serial ATA ports installed, as a result, an Intel USB flash disk is used instead of a hard disk drive. Although the mainboard seems to fit into a typical computer case, it does not look like it complies with ATX specification.
Mainboard of Intel 48-core SCC prototype system.
During the event in Europe, the SCC – covered by a rather advanced cooling system – was up and running with all of its quad-channel controllers operating, which may indicate that the processor was showcased in all its glory.
Intel was demonstrating multiple applications running on the SCC, including a workload that shows the advanced power management capabilities and a parallel application that uses a standard MPI as the communication layer. It can be seen from the photo, Intel also demonstrated formation of fractals using Mandelbrot set, however, since the software was proprietary, no performance numbers are available.
According to Intel, the 48-core chip operates at the clock-speed comparable to Intel Atom microprocessors, which means that the frequency of the microprocessors is in the range between 1.60GHz and 1.83GHz.
The prototype chip contains 24 tiles with two x86 cores per each, which results in 48 cores – the largest number ever placed on a single piece of silicon. Each core can run a separate OS and software stack and act like an individual compute node that communicates with other compute nodes over a packet-based network. Every core sports its own L2 cache and each tile sports a special router logic that allows tiles to communicate with each other. A 24-router mesh network with 256GB/s bisection bandwidth. The processor sports four integrated DDR3 memory controllers, or one controller per twelve cores.
Though each core has 2 levels of cache, there is no hardware cache coherence support among cores in order to simplify the design, reduce power consumption and to encourage the exploration of datacenter distributed memory software models on-chip.
The SCC can run all 48 cores at one time over a range of 25W to 125W and selectively vary the voltage and frequency of the mesh network as well as sets of cores. Each tile (2 cores) can have its own frequency, and groupings of four tiles (8 cores) can each run at their own voltage.
One of the distinct features of the new 48-core experimental chip is its extreme programmability. Software applications will be able to automatically control the number of cores to use at any given time and operating systems will be able to assign certain cores for auxiliary tasks. Moreover, software will be able to manage power consumption, clock-speed of individual cores or even shut them down when not needed.
The experimental 48-core CPU will help Intel and software developers to study management and scheduling mechanisms of explicitly multi-core microprocessors in order to get prepared to bring them onto the mass market. Next year, Intel plans to provide software developers more than a hundred of experimental chips for development of new software apps.