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During the International Supercomputing Conference (ISC), Intel Corporation announced plans to deliver new products based on the Intel many integrated core (MIC) architecture that will create platforms running at trillions of calculations per second, while also retaining the benefits of standard Intel processors.

Targeting high-performance computing segments such as exploration, scientific research and financial or climate simulation, the first product, codenamed "Knights Corner”, will be made on Intel's 22nm manufacturing  process and will use Moore's Law to scale to more than 50 Intel processing cores on a single chip. While the vast majority of workloads will still run best on Intel Xeon processors, Intel MIC architecture will help accelerate select highly parallel applications.

"Intel's Xeon processors, and now our new Intel Many Integrated Core architecture products, will further push the boundaries of science and discovery as Intel accelerates solutions to some of humanity's most challenging problems. The Intel MIC architecture will extend Intel's leading HPC products and solutions that are already in nearly 82 percent of the world's top supercomputers. Today's investments are indicative of Intel's growing commitment to the global HPC community," said Kirk Skaugen, vice president and general manager of Intel's data center group.

Industry design and development kits codenamed "Knights Ferry" are currently shipping to select developers, and beginning in the second half of 2010, Intel will expand the program to deliver an extensive range of developer tools for Intel MIC architecture. Common Intel software tools and optimization techniques between Intel MIC architecture and Intel Xeon processors will support diverse programming models that will place unprecedented performance in the hands of scientists, researchers and engineers, allowing them to increase their pace of discovery and preserve their existing software investments. The Intel MIC architecture is derived from several Intel projects, including "Larrabee" and such Intel Labs research projects as the Single-chip Cloud Computer (SCC).

"The CERN openlab team was able to migrate a complex C++ parallel benchmark to the Intel MIC software development platform in just a few days. The familiar hardware programming model allowed us to get the software running much faster than expecte,” said Sverre Jarp, chief technology officer of CERN openlab.

To meet the growing challenge of running large-scale simulations in the multi petaflops and exaflops range of computing, Intel, Forschungszentrum Julich (FZJ) and ParTec will announce a multi-year commitment to create the ExaCluster Laboratory (ECL) at Julich. The lab will develop key technologies, tools and methods to power multi petaflops and exaflops machines, focusing on the scalability and resilience of those systems. ECL will become the latest member of Intel Labs Europe, a network of research and innovation centers spanning Europe.

Tags: Intel, x86, Larrabee, SCC, MIC

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