Advanced Micro Devices will disclose more details about its forthcoming code-named Bulldozer micro-architecture at Hot Chips conference in late August. Potentially, micro-architectural details may reveal projected performance of the forthcoming multi-core central processing units.

In the program of the Hot Chips conference AMD itself describes Bulldozer core as “a new approach to multithreaded compute performance for maximum efficiency and throughput”, which means that the forthcoming core does include a multi-threaded technology, which may be completely different from implementations from companies like Intel Corp. or Sun Microsystems. AMD plans to present the Bulldozer details on the 24^th of August, 2010.

Based on the information provided by AMD during its annual Analyst Day last November, the first Bulldozer chip code-named Zambezi (which belongs to Orochi family, according to the firm) will feature eight x86 processing engines with multithreading technology, two 128-bit FMAC floating point units, shared L2 cache, shared L3 cache as well as integrated memory controller. AMD also states that the new CPU will feature “extensive new power management innovations”. The new chips that belong to Bulldozer family will also support Advanced Vector Extensions (AVX) that support 256-bit FP operations.

Based on a diagram that AMD demonstrated in the past, the company intends to dramatically improve multithreading performance of its CPUs with the help of two INT schedulers, an FP scheduler and separate data caches for each of four cores should do the job very well.

AMD has not released any data regarding performance of Bulldozer chip, but since the chip designer positions the unit as a solution for high-end desktop and server solutions in 2011, it does expect this 32nm SOI with high-k metal gate power-house to be a high-performer.

Tags: AMD, Bulldozer, Zambezi, Orochi, , SSE5, AVX, 32nm