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Intel Corp. has disclosed specifications of its test vehicle for MIC (many Intel cores) accelerators aimed at servers. The first one - code-named Knights Ferry - seems to resemble infamous Larrabee graphics processing unit.

The Knights Ferry has 32 x86 cores clocked at 1.2GHz and featuring quad-HyperThreading. The unit, aimed at PCI Express 2.0 slots, has up to 2GB of GDDR5 memory. The chip itself has 8MB of shared L2 cache, which is quite intriguing by itself since highly-parallel applications do not require a large on-chip cache. Intel did not unveil raw computing performance of the Knights Ferry in GigaFLOPS or TeraFLOPS.

Given the fact that Knights Ferry is not a commercial product, but a development platform, it is unclear whether it has similar micro-architectural peculiarities as the Knights Corner chip, which is designed to be sold to interested parties. The Knights Corner will initially target high-performance computing segments, such as exploration, scientific research and financial or climate simulation. The chip will be made on Intel's 22nm manufacturing  process and will have more than 50 Intel processing cores on a single chip. Intel itself stresses that neither KF nor KC are set to substitute traditional server processors since "the vast majority of workloads will still run best on Intel Xeon processors", whereas Intel MIC architecture will help accelerate select highly parallel applications.

Intel insists that even for high performance computing (HPC) compatibility with x86 instruction set is a benefit. Meanwhile, both AMD and Nvidia are selling their proprietary FireStream and Tesla to HPC customers. Typically HPC applications are created for exact hardware, which is why compliancy with certain instruction sets is not that important.

The Intel MIC architecture is derived from several Intel projects, including "Larrabee" and such Intel Labs research projects as the Single-chip Cloud Computer (SCC).

Tags: Intel, GPGPU, Larrabee, SCC, Knights Corner, Tesla, FireStream, x86, Knights Ferry


Comments currently: 12
Discussion started: 08/08/10 04:36:43 PM
Latest comment: 08/12/10 03:15:34 AM
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You know, I'm 90% sure they ARE slightly modified Larrabee cores. Just like Nvidia's Fermi, the GPU and CPU functions are very similar.
0 0 [Posted by: siuol11  | Date: 08/08/10 04:36:43 PM]

How could it be a Larrabee with quad hyper threading per core? The Larrabee was based on the Pentium MMX, and only had two pipes, and one did very little.

I wish they would kill x86, it's not worth it for this type of thing.
0 0 [Posted by: TA152H  | Date: 08/08/10 07:03:49 PM]
- collapse thread

and replace it with what the Itantic? Intel tried going off x86 and no one was interested. It's far to expensive and time conusimg to rewrite all the software people use to run on a new architecture.
0 0 [Posted by: sollord  | Date: 08/08/10 08:54:11 PM]
You don't need it for something like this.
That's the problem, Intel tries to move x86 into new markets, and the handicaps aren't worth the benefits.
0 0 [Posted by: TA152H  | Date: 08/10/10 04:37:59 AM]
Intel not look like suicide company to move from x86.
0 0 [Posted by: Blackcode  | Date: 08/11/10 12:48:20 PM]

Seriously Anton. This is the BEST example of delayed news. The same news has been spammed by other review sites 3 months ago.

Knights Ferry is Larrabee.

Stop polluting the internet with news so old that's a legend in computer terms.

BTW, there's no such thing as "Quad Hyperthreading". Correct way would be 4-way Hyperthreading.

TA152H: Larrabee is "based" on Pentium MMX not equal to Pentium MMX. If you think many core designs are regular CPUs copied and pasted like you do on MS Word, you shouldn't be posting anything about it. It's been known about forever Larrabee is a 4-way multi-threading core.
0 0 [Posted by: DavidC1  | Date: 08/09/10 07:03:53 AM]
- collapse thread

agreed ... this is what a real life news supposed to look like and it was late May 2010 (so only 2.5month behind)

and disagree about your claim that Larabee cores aren't just Pentium Overdrive (P54) cores + additional 512bit vector crunching FPU.
0 0 [Posted by: OmegaHuman  | Date: 08/10/10 03:47:15 AM]
That's like saying a cow is based on a cat. You start with it, give it retractable claws, make it lose body fat, make it faster, give it sharp teeth to pierce flesh, make it very agile, etc...

And it's based on a cat?

The Pentium MMX had one real pipeline. The second, the "V", couldn't execute many instructions. Now you're saying something that can issue four instructions to this is based on it? What???? By that point, it's no longer anything like a Pentium.
0 0 [Posted by: TA152H  | Date: 08/10/10 04:40:53 AM]

What a perv name for that Larabee chip, but interestig par is how that cores are only capable of 4 parallel threads whaen LRB1 support 512bits so it should be as announced at least 16 32-bit threads or 8 x86-64 threads. Probably original LRB vector mask is not nearly implemented in this Knight chips and this way chip consumes far less than ridiculous 300W+ while having mediocre performance, even LRNB wasnt some excellent performer.

It's probably here to make negative impact with its under performance to next generation Bulldozer chips (and should make us questioning of Sandy Bridge performance)
0 0 [Posted by: OmegaHuman  | Date: 08/10/10 02:11:39 AM]
- collapse thread

Sigh. Relating 512-bit SIMD on LRB to x86-64....
0 0 [Posted by: DavidC1  | Date: 08/10/10 02:23:58 AM]

Probably aim to Bulldozer ,because Bulldozer should support CMP and JMP instructions (fusion)?
0 0 [Posted by: Blackcode  | Date: 08/11/10 12:34:54 PM]

the Knight Ferry > Fushion
0 0 [Posted by: BHD  | Date: 08/12/10 03:15:34 AM]


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