Intel Corp. has announced the launch of the MARC (many-core applications research community) initiative, which will explore next-generation software. The programs will be initially written for Intel 48-core single-chip cloud computer (SCC) that has a number of peculiarities completely different from the contemporary central processing units.
Under the new MARC program, academic and industry researchers will be able to use the SCC as a platform for next-generation software research. The MARC initiative will be headed by Sebastian Steibl, head of Intel Labs Braunschweig. Today MARC consists of more than 50 research projects from 38 institutions worldwide, including over 20 institutions from Europe, with dozens more in the process of finalizing membership contracts.
The European component of the community will be driven by Intel Labs Braunschweig, a member of the Intel Labs Europe network and whose researchers co-led the development of the SCC. The researchers can use the 48-core research processor to speed up the development of the next generation of applications and software for multi-core processors (parallel programming). These programs should one day lead to dramatic new computing experiences for people and business. The SCC was introduced at the end of last year.
"Although MARC has been launched with an initial focus on the SCC concept vehicle, we hope that the community itself proves to be as valuable as the chip. As such, we will explore sharing other hardware and software research platforms over time," a statement by Intel reads.
Intel engineers from Braunschweig have now contributed to most of the current processor lines. During the course of the 10th anniversary celebrations, a new project was announced, in which the team from Braunschweig, in collaboration with various Intel developer teams throughout the world, is now working on future processor architectures with special focus on energy-efficiency.
The SCC prototype chip contains 24 tiles with two x86 cores per each, which results in 48 cores – the largest number ever placed on a single piece of silicon. Each core can run a separate OS and software stack and act like an individual compute node that communicates with other compute nodes over a packet-based network. Every core sports its own L2 cache and each tile sports a special router logic that allows tiles to communicate with each other using a 24-router mesh network with 256GB/s bisection bandwidth. There is no hardware cache coherence support among cores in order to simplify the design, reduce power consumption and to encourage the exploration of datacenter distributed memory software models on-chip. Each tile (2 cores) can have its own frequency, and groupings of four tiles (8 cores) can each run at their own voltage. The processor sports four integrated DDR3 memory controllers, or one controller per twelve cores.
Intel calls x86 cores inside the SCC as “Pentium-class” cores since they are superscalar in-order execution engines, but stresses that those are not cores used inside by the original Pentium (P5) processors since they have been enhanced in order to achieve certain goals and make the design suitable for implementation into the experimental chip. Considering that SCC lacks any floating point vector units, raw horsepower of the chip is relatively weak.
Intel SCC is not supposed to become an actual product by definition. The design, peculiarities and single-thread performance of the prototype will hardly satisfy actual users. The chip is purely a prototype that will help Intel and software developers to determine directions for future development of the microprocessors and software.