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The eight-core microprocessors from Advanced Micro Devices based on the Bulldozer micro-architecture that feature Orochi design will get massive internal cache systems compared to current-generation of chips. In total, the top-of-the-range single-die processor will have 16MB of cache.

AMD Orochi chip (which is a universal server and client design that will power Valencia, Zambezi and possibly other implementations of first-gen Bulldozer family) will have 8MB unified level-three cache, according to a document seen by X-bit labs. Since eight-core Orochi features four dual-core Bulldozer modules, each of which is believed to have 2MB of shared level-two cache, the whole chip will pack in whopping 16MB of SRAM, a 77% increase from the current six-core microprocessors that have 9MB of cache in total.

Large L2 caches will help AMD's next-generation microprocessors to ensure higher performance in single-threaded applications compared to today's multi-core chips that only have 512KB of L2, whereas massive L3 cache will maximize memory bandwidth. In both cases this will bring notable performance gains compared to today's Stars/Greyhound architecture.

AMD Orochi design is the company's next-generation processor for high-end desktop and server markets. The chip will feature eight processing engines, but since it is based on Bulldozer micro-architecture, those cores will be packed into four modules. Every module which will have two independent integer cores (that will share fetch, decode and L2 functionality) with dedicated schedulers, one floating point unit with two 128-bit FMAC pipes with one FP scheduler. The chip will have shared L3 cache, new dual-channel DDR3 memory controller and will use HyperTransport 3.1 bus. The Orochi chips will use new AM3+ form-factor and will require brand new platforms.

AMD did not comment on the news-story.

Tags: AMD, Bulldozer, Zambezi, Orochi, Interlagos, Valencia, Phenom, Athlon


Comments currently: 4
Discussion started: 09/23/10 06:41:17 PM
Latest comment: 09/25/10 09:42:55 PM
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This has been known for going on a year now...

I can't remember whom reported it first, Dresdenboy, hardware-infos, or whomever.
0 0 [Posted by: turtle  | Date: 09/23/10 06:41:17 PM]

I was late by a day . I reported it in this posting in January.

And that was based on a posting in RWT's forum.

The cache info itself appeared in the Open64 compiler source. This still lacked L3 cache info. And it was no official information. The 16kB L1 became official at Hot Chips. And the 2MB L2 per module once slipped into JF's Q&A blog. I think the L2 and L3 sizes still have to be made official.

But looking at the Orochi die, as also shown on X-bit labs, one could already see the 2MB L2 per module and four blocks of 2MB L3 on the die.
0 0 [Posted by: Dresdenboy  | Date: 09/24/10 12:09:41 AM]

AMD seems to believe that cache makes up for everything. They did so when launching Phenom II and I hope that, this time, they've really improved the IPC and the intrinsic architecture.
0 0 [Posted by: East17  | Date: 09/25/10 04:04:24 AM]
- collapse thread


They're not Intel to think that way

But rightfully they acquired same sharky business methods as Intel did with their marketing scheme pushing enormous caches back in 2001-2006 when they couldn't make decent chip

It'll be nice to see how much L3 cache Sandy Bridge will sport against Orochi (codename:Bulldozzer) because they suppose to be comparable chips with similar feature sets so we could have better insight how large cache helps them in their number crunching.
0 0 [Posted by: OmegaHuman  | Date: 09/25/10 09:42:55 PM]


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