At the Intel Developer Forum (IDF) the world's largest maker of microprocessors provided an update on the progress of the Intel Many Integrated Core (Intel MIC) architecture for high-performance computing segments. Intel plans to launch its first MIC product on Intel’s upcoming 22nm process technology and expects to have more than 100 developer sites for MIC by the end of 2011.
The add-on accelerators Intel MIC micro-architecture are expected to be used for highly parallel applications in high performance computing segments such as scientific exploration and research, weather modeling and other. But MIC - just like existing AMD FireStream or Nvidia Tesla solutions - will not replace processors like AMD Opteron or Intel Xeon, but will accelerate special applications only. Even though at present developers use proprietary tools to take advantage of Tesla or FireStream pretty successfully, as the world's No. 1 supercomputer now uses Nvidia Tesla along with Intel Xeon chips, Intel insists that x86 compatibility with x86 will give it unique advantages.
"Think about Intel MIC as a co-processor. The advantage here is that you can use the same compilers, the same tools, the same [Intel] VTunes [performance profilers] that power around 90% of the Top 500. The next generation you run the compiler, it will optimize the workloads for the Intel cores, that are in the Xeon CPUs, and it will optimize on these new PCI Express cards that will have more than 50 cores and be on our 22nm process technology. So it will automatically balance that workload for the highest-parallel workloads on the planet," Kirk Skaugen, vice president of the Intel architecture group and general manager of Intel's data center group, during his keynote at the Intel Developer Forum (IDF).
So far Intel has supplied code-named Knights Ferry MIC test platform to select developers and plans to expand the number of developers, who can have the hardware, to one hundred by the end of 2011. While the number seems to be large, it is negligible compared to access to Nvidia's CUDA highly-parallel software development platform, which is available for everyone. Back in 2010 the company indicated that 600 thousand CUDA toolkits had been downloaded.
"We are going to be expanding for you as software developers this to over 100 end-users by the end of the year, so you can begin experiencing the incredible performance here. We had a male clinic take products and codes used to run in several minutes and get them down to 10 - 20 seconds. We had CERN, one of the largest particle accelerators, take code that had traditionally been run on Xeon and within 4-5 hours [of optimization work] it was running three times faster that they had ever seen on any architecture on the planet. This is a very revolutionary architecture, it is incremental to what we are doing with Xeon and Itanium," said Mr. Skaugen.
According to Intel, development is on track to deliver the "leading" software programming model for highly parallel workloads.
Tags: Intel, MIC, Knights Ferry, Knights Corner, Tesla, FireStream, CUDA, Larrabee
Comments currently: 5
Discussion started: 04/14/11 10:51:59 AM
Latest comment: 04/16/11 01:02:41 AM
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AMD can make it using bulldozer arch or not...???
04/14/11 10:51:59 AM]
This sounds to me like Intel is leveraging it's process technology (and others' stumbling towards thereof) to fit a square peg in a round hole. They have a small time-frame to push this and hope it catches on, imo; Between when they can create a large 22nm chip (I'm guessing 64 - x cores for yield), and when AMD/nVIDIA can ship a decent-sized 28nm chip (IE, I'm not counting the initial AMD 28nm parts). It NEEDS to be 40nm (or small 28nm chips) versus 22nm for Intel to make this feasible, at least judging by Larrabee. That gives them at most a year, probably less.
It's been pretty-well dissected that when GPUs (from AMD/nVIDIA) and Intel's MIC technology are on the same or similar process, Intel's architecture cannot keep pace in parallel computing. More than once I've seen LRB compared to a mid-range (to low-end) GPU. They can leverage X86, sure, but why isn't that code simply ported to CUDA/Stream? It appears very jack-of-all-trades. While that's great for consumer products, not-so in the HPC sector.
If for whatever reason this gets off the ground, and it may, I hope they establish a reasonable standard. While Intel may be simply laying a groundwork for things to come in upcoming CPU generations, I pray we can see compatibility when AMD folds 'stream processors' into their CPU cores for floating point operations as well. Both players are headed in the same direction...let's hope Intel does us right by putting their toes in parallel+86 water first.
04/14/11 01:03:42 PM]
Their uptake would be a lot higher if they support OpenCL.
I think that MIC will have serious advantages for applications that sit between GPU and CPU.
I'd imagine wanting both in a system and optimising what parts of an algorithm runs best on which. This already occurs between the CPU and GPU for some applications.
i.e. Write it all in OpenCL.
For tasks that have highly irregular memory access and complex program flow run on the CPU. Those task that have very streamed memory flow and very little branching run on the GPU. Anything in between runs on the MIC.
04/14/11 08:41:48 PM]
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I'm not sure. The programming model for MIC is actually quite a bit simpler than programming with OpenCL. If they can be at least competitive on the hardware side, the software side could push them ahead.
04/15/11 09:22:36 PM]
Exactly. OpenGL and GPU's in general suffer because their programming model is very specialised. That makes them hard to use for many applications.
04/16/11 01:02:41 AM]
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